Solid-State Lighting (SSL) applications are slowly but gradually pervading into our daily life. An SSL system is composed of an light-emitting diode (LED) engine with a microelectronic driver(s) in a housing that also supplies the optic design. Knowledge of system-level reliability is crucial for the business success of future SSL systems, and also a very scientific challenge. In practice, a malfunction of the system might be induced by the failure and/or degradation of the subsystems/interfaces. Extra costs, in terms of exceed efforts/designs/parts, have been applied to the systemin order to secure the guaranteed reliability performance of SSL system. Most SSL system designs allow few failures of the subsystem/interface during the application period. Hence, a significant cost reduction can be achieved when the system-level reliability is well understood by proper experimental and simulation techniques. This chapter covers the reliability of total SSL systems including the reliability theories and practices for all (sub) components, such as LED engines, drivers, and fixtures.

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Reliability is an important aspect of LED-based systems and modules, as long lifetime is an important selling argument. Besides, LED modules are specific solutions for specific applications. As a result of the strong customization, reliability estimations for LED-based modules start practically from scratch. Therefore there is a need for a generic system level reliability approach for lifetime and reliability estimations of LED systems. This paper describes our approach to determine system reliability based on the known failure distributions of the sub-components.@en

An increasing number of semiconductor companies have research programs related to MEMS products. This can be explained by the wide variety of application areas for MEMS, some mechanical MEMS examples are: filters [1], oscillators [2,3], pressure sensors [4], particle detection [5], thermometers [6] and gyroscopes [7]. Many mechanical MEMS operate in vacuum and sealing of the cavity can be obtained by using a wafer level thin film package or zero level package. Such a package consists of a thin film cap, which is released by etching away a sacrificial layer, and a sealing structure. The main advantage of this method towards others such as local assembly is that all caps can be made in one time and the small scale of the sealing. To fit a MEMS into a small (plastic) package the die needs to be processed in several steps. Examples are: wafer thinning and dicing. In earlier research it was shown that wafer thinning is one of the potentially more hazardous assembly processes due to the large mechanical forces exerted on the wafer [8]. This paper presents an extensive DOE to assess the performance of Wafer Level Thin Film Packages (WLTFP¿s) under assembly processes . The influences of the wafer thinning process on a large variety of WLTFP¿s are quantified. A selection of relevant samples is also tested in other key assembly steps like dicing, die-attach and moulding.@en

Thin metal films are widely used in modern electro mechanical systems. The need for more integrated functionality and minimization of material and energy consumption leads to miniaturization of these systems. As a consequence, materials are processed on the micro- and nanometer scale. On this scale, material properties become a function of size. To predict performance and reliability, knowledge on the size dependence of material properties is imperative. In this work the unknown size dependence of the copper Young's modulus is determined by electrostatic pull-in experiments performed on bilayer copper-silicon nanocantilevers. The size effect is also predicted with a multi-scale (MS) method. In this method atomistic simulations predict the bulk elastic and surface properties of mono-crystalline silicon (Si) and poly-crystalline copper (Cu). These results are combined to represent the bilayer nanocantilevers of the experiment in a continuum model. The model is verified by comparison with a well documented size effect of the effective Si Young's modulus. It is shown that the experimental method can be used for determining the Young's modulus of thin Cu films in the 10 to 50 nm range. Both the experimental results and the MS simulation results show that there is a strong size effect present in Si and Cu.@en

An increasing number of semiconductor companies have research programs related to MEMS resonators. This can be explained by the possible wide range of application areas. Many resonators operate in vacuum and sealing of the cavity can be obtained by using a Wafer Level Thin Film Package (WLTFP). To fit the MEMS-die into a small package it needs to be thinned. In this paper the effect of wafer thinning on the WLTFP is investigated by means of simulation and experiments. The effects of tape removal on WLTFP's are simulated in 2 and 3 dimensions using the cohesive zones technique. Necessary adhesive properties of the grinding foil are measured by a grinding tape peeling experiment. In 2D FE simulation damage is included to predict the most likely cracking path.@en

Wafer Level Packages are one of the most advanced packaging concepts. It combines the advantages of flip chip with conventional surface mount technologies. In recent years, we have seen a tremendous growth in the application of Wafer Level Packages, both in quantities as well as in the number of products where they are implemented. The technology is, however, not without its challenges with 1st and 2nd level reliability issues. For instance, the limit on the size of Wafer Level Packages has to do with the 2nd level, or solder bump, reliability. This paper highlights our major research and development results on understanding and enhancing the 1st and 2nd level reliability of Wafer Level Packages using combined experimental and virtual prototyping (thermal, mechanical and thermo-mechanical) techniques. Typical 1st level reliability problems within Wafer Level Packages are cracking of repassivation materials, fatigue of bond over active pads, and cracks within the Under Bump Metalisation. Typical 2nd level problems concern solder fatigue and brittle fractures within the intermetallics. To investigate the physics of failure for these problems, dedicated parametric finite element models are constructed including the thin IC layers. Two structures are explored to their potential reliability benefits, being the traditionally used repassivation structure and a newly developed Bump on Active structure. This so-called BUMA structure makes use of a thick A1 buffer layer. By combining the experimental results with reliability prediction models, both structures in terms of 1st and 2ne level reliability performance are explored. Based on the results we have designed and manufactured an improved construction that significantly outperforms current solutions.@en

This paper discusses the assembly challenges considering the design and manufacturability of a Wafer Level Thin Film Package in MEMS applications. The assembly processes are discussed. The loads associated with these processes are illustrated and evaluated. Numerical calculations are combined with experimental observations in order to estimate the assembly risks. Our results emphasize the need for concurrent design for assembly. Keywords: MEMS; wafer level thin film package; packaging; resonator@en

With the ever-growing number of MEMS resonator applications, a research effort is required. One important step to consider in the design and evaluation phase is the packaging of such a resonator.@en

In the growing MEMS market Wafer Level Thin Film Packages can be applied to an increasing numer of MEMS devices. This paper discusses the effects of common assembly processes on wafer level thin film packages. All assembly processes are discussed and the effects of the process on the structures is presented. From the assembly tests the grinding process poses the largest hazards followed by dicing, moulding, wire bonding and finally die attachment. A number of improvements related to etch holes and sealing structures are proposed to enhance the crack resistance and robustness.@en

The use of microelectronic components in mobile appliances is constantly increasing. Appliances like mobile phones, PDA's and navigation systems contain more and more functionality and smaller microelectronic components.@en

The increased use of mobile appliances such as mobile phones and navigation systems in today's society has resulted in an increase in reliability issues related to drop performance. Mobile appliances are dropped several times during their lifespan and the product is required to survive common drop accidents. A widely accepted method to assess the drop reliability of microelectronics on board-level is the drop impact test. this test had been standardized by international councils such as Joint Electron Device Engineering Council and is widely adopted throughout the industry. In this research the solder loading is investigated by combining high-speed camera measurements of several drop impact tests with verified finite element models. These simulation models are developed in order to gain an insight in the loading pattern of solder joints based on interconnect layout, drop conditions, and product specifications prior to physical prototyping. Deflections and frequencies during drop testing are measured using a high-speed camera setup. The high-speed camera experiments are performed on two levels: machine level (rebounds with and without a catcher) and product level (with different levels of energy and different pulse times). Parametric (dyanamic and quasistatic) 3D models are developed to predict the drop impact performance. The experimental results are used to verify and enhance the simulation models, e.g. by tuning the damping parameters. As a result, the verified models can be used to determine the location of the critical solder joint and to obtain estimates of the solder lifetime performance. Keywords: drop impact reliability, drop impact modeling, chip scale packages, high-speed camera experiment.@en

With the increased use of mobile phones, navigation systems, PDA's, laptops and portable gaming devices, the drop reliability of microelectronics has become an important parameter. Assessing the solder interconnect quality by means of drop impact testing, as standardized by e.g. JEDEC, during normal production requires considerable amounts of time and effort. Besides this, the repeatability of the drop impact test is low and introduces elaborate and time-consuming analysis of the results after testing. Already many researchers have investigated new test techniques capable of replacing the drop impact test, e.g. high-speed shear, pull and bending. Among those tests is the High Speed Cold Bump Pull test (HSCBP or CBP). In the CBP test the solder bump is pulled in vertical direction from the die using a smal pair of jaws. In this test, by varying the pull speed several different strain-rates can be applied to the solder bump. In our research a correlation between the drop impact test and cold bump pull test is investigated. This can be divided into three parts. First by investigating the cold bump pull test apparatus for uncontrolled parameters that might introduce a bias or spread in the results. Secondly by means of modeling the cold bump pull test to investigate solder bump deformation and solder bump loading during pull-off. Finally, the differences and simularities between the drop impact test and the cold bump pull test are briefly discussed and some observations concerning the solder joint performance are presented.@en

The increased use of mobile applicances in today's society has resulted in an increase of reliability issues related to drop performance. Mobile appliances are dropped multiple times during their lifespan and the product is required to survive common drop accidents. The use of lead-free solder compositions and the decreasing size of microelectronics aggravated the sensitivity of these products towards drop failures. Also, the use of miniature IC packages like Wafer Level Chip Scale Packages (WLCSP) with smaller lead sizes resulted in a decreased amount of material available to absorb the loading caused by a drop. A widely accepted method to assess the drop reliability of microelectronics on board-level is the drop impact test. The drop impact test has been standardized by international councils like JEDEC and is widely adopted throughout the industry. The intention of the drop test is to assess the overall product reliability towards dropping, focusing on the solder interconnections. These solder interconnections are usually the first link in the chain to fail. Clearly the drop impact reliability of a product is also influenced by numerous design factors like material compositions, ball layout and product size as well as manufacturing conditions. Solder loading is investigated in this research by using high-speed camera recordings of several drop impact tests with verified Finite Element models. These simulation models are developed in order to gain an insight on the loading pattern of solder joints based on product specifications, interconnect layout and drop conditions prior to physical prototyping. Deflections and frequencies during drop testing are measured using a high-speed camera setup. The high-speed camera experiments are performed on two levels: product level (with different levels of energy and different pulse times) and machine level (rebounds with and without a catcher). Parametric (dynamic and quasi static) 3D models are developed to predict the drop impact performance. The experimental results are used to verify and enhance the simulation models, e.g. by tuning the damping parameters. As a result, the verified models can be used to determine the location of the critical solder joint and to obtain estimates of the solder lifetime performance.@en

The increased use of mobile appliances in today's society has resulted in an increase of reliability issues related to drop performance. A common method to assess the drop performance is the JEDEC specified drop impact test [1]. In this research the solder loading is investigated by means of drop impact simulations and high-speed camera measurements. The measurements are used to enhance the simulations by tuning the damping parameters. This results in models that are replicating the drop impact amplitudes and are thereby capable of determining the critical solder joint.@en

The use of microelectronic components in mobile appliances is constantly increasing. Appliances like mobile phones, PDA's and navigation systems contain more and more functionality and smaller microelectronic components. Dropping an appliance during its lifespan is very common and the product is required to survive this. The drop however generates significant forces and vibrations on the internal assembly of the product. The performance of a microelectronic component under drop conditions has thus become an important reliability parameter. Assessing the solder interconnect quality by means of drop impact testing, as standardized by e.g. JEDEC, during normal production requires considerable amounts of time and effort. Besides this, the repeatability of the drop impact test is low and introduces elaborate and time-consuming analysis of the results after testing. Already many researchers have investigated new test techniques capable of replacing the drop impact test, e.g. high-speed shear [1], pull [2] and bending. Among those tests is the High Speed Cold Bump Pull test (HSCBP or CBP). In the CBP test the solder bump is pulled in vertical direction from the die using a small pair of jaws. In this test, by varying the pull speed several different strain-rates can be applied to the solder bump. In our research a correlation between the drop impact test and cold bump pull test is investigated. This can be divided into three parts. First by investigating the cold bump pull test apparatus for uncontrolled parameters that might introduce a biass or spread in the results. Secondly by means of modeling the cold bump pull test to investigate solder bump deformation and solder bump loading during pull-off. Finally in a comparison the differences and similarities between the two tests are briefly discussed and some observations concerning the solder joint performance are presented. The correlation between the two tests is focused on a method capable of translating the loading conditions experienced in the drop impact test towards a cold bump pull test prescription. Several numerical simulations have been used to investigate the solder ball during deformation and destruction. The cold bump pull experiments are used to rule out as much variances as possible and improvements for the cold bump pull apparatus are proposed.@en