A 20-bit incremental ADC for battery-powered sensor applications is presented. It is based on an energy-efficient zoom ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine 15-bit ΔΣ conversion. To further improve its energy efficiency, the ADC employs integrators based on cascoded dynamic inverters for extra gain and PVT tolerance. Dynamic error correction techniques such as auto-zeroing, chopping and dynamic element matching are used to achieve both low offset and high linearity. Measurements show that the ADC achieves 20-bit resolution, 6 ppm INL and 1 μV offset in a conversion time
of 40 ms, while drawing only 3.5 μA current from a 1.8 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 182.7 dB. The 0.35 mm² chip was fabricated in a standard 0.16 μm CMOS process.@en

This paper describes an energy-efficient CMOS temperature sensor intended for use in RFID tags. The sensor achieves an inaccuracy of ±0.15°C (3σ) over the military temperature range (-55 to 125°C) and dissipates only 27nJ/conversion: over 20× less than a previous sensor with comparable accuracy and resolution [2]. This energy efficiency is achieved by the use of an improved charge-balancing scheme and a zoom ADC that combines a 5b coarse SAR conversion with a 10b fine 2 nd -order ΔΣ conversion.@en

This paper presents a 20-b read-out IC with ±40-mV full-scale range that is intended for use with bridge transducers. It consists of a current-feedback instrumentation amplifier (CFIA) followed by a switched-capacitor incremental ΔΣ ADC. The CFIA's offset and 1/ f noise are mitigated by chopping, while its gain accuracy and gain drift are improved by applying dynamic element matching to its input and feedback transconductors. Their mismatch is reduced by a digitally assisted correction loop, which further reduces the CFIA's gain drift. Finally, bulk-biasing and impedance-balancing techniques are used to reduce the common-mode dependency of these transconductors, which would otherwise limit the achievable gain accuracy. The combination of these techniques enables the read-out IC to achieve 140-dB CMRR, a worst-case gain error of 0.04% over a 0-2.5 V common-mode range, a maximum gain drift of 0.7 ppm/°C and an INL of 5 ppm. After applying nested-chopping, the read-out IC achieves 50-nV offset, 6-nV/°C offset drift, a thermal noise floor of 16.2 nV/√Hz and a 0.1-mHz 1/ f noise corner. Implemented in a 0.7-μm CMOS technology, the prototype read-out IC consumes 270 μA from a 5-V supply.@en