This paper presents an extensive characterization of the low-frequency noise (LFN) at room temperature (RT) and cryogenic temperature (4.2 K) of 40-nm bulk-CMOS transistors. The noise is measured over a wide range of bias conditions and geometries to generate a comprehensive overview of LFN in this technology. While the RT results are in-line with the literature and the foundry models, the cryogenic behavior diverges in many aspects. These deviations include changes with respect to RT in magnitude and bias dependence that are conditional on transistor type and geometry, and even an additional systematic Lorentzian feature that is common among individual devices. Furthermore, we find the scaling of the average LFN with the area and its variability to be similar between RT and 4.2 K, with the cryogenic scaling reported systematically for the first time. The findings suggest that, as no consistent decrease of LFN at lower temperatures is observed while the white noise is reduced, the impact of LFN for precision analog design at cryogenic temperatures gains a more predominant role.

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Quantum computers promise large speedups compared to classical computers for specific classes of problems by exploiting quantum phenomena for computation. Despite notable progress towards larger systems, today's quantum computers still lack the necessary size for realizing many of the anticipated benefits. Scaling to these larger numbers is complicated by the fragility of the qubits, which raises the necessity of operating the quantum computing core at deep cryogenic temperatures to limit the influence of noise. However, in the present experimental setups for quantum computing the electronic interfaces are often based on equipment operated at room temperature. This arrangement creates a potential wiring bottleneck towards cryogenic temperature, that is connected to reliability limitations. A proposed solution to this challenge is moving the interfacing electronics close to the qubits into the cryogenic environment. However, implementation of the electronics at cryogenic temperature places a set of system constraints that prevents directly porting the room-temperature electronics. The most prominent of these constraints is the limited cooling power at deep cryogenic temperature, requiring the interfacing electronics to save power wherever possible. To implement the necessary functions of the interface in practice, CMOS technology is uniquely positioned due to its large scale integration capabilities, low-power digital logic and sustained performance at cryogenic temperature.

In this work, contributions to the readout electronics of quantum computers are made, with an emphasis on the readout of semiconductor spin quantum computers. Readout poses a significant challenge for current spin-qubit systems, especially its scalable integration into the electronic interface. This dissertation can be separated into contributions to the readout of quantum computers in three main categories: cryogenic digitization, cryogenic noise characterization and readout benchmarking.

The wide-band signals present in the frequency-multiplexed RF readout interface require corresponding wide-band digitization capabilities of the associated data converters. In this work, we present robust, power-efficient and high-speed time-interleaved SAR ADC designs adopted to operation at cryogenic temperature to serve this application. These include the first high-speed cryo-CMOS SAR ADC suitable for operation in the RF readout interface, further efficiency improvements to this ADC and finally an ADC tightly integrated with an efficient body-bias enabled dynamic pre-amplifier. The body-bias enabled pre-amplifier also demonstrated excellent room-temperature performance, with the best reported combined power efficiency of a high-speed SAR and driver circuit.
All designs have been realized in a 40nm CMOS technology and characterized at cryogenic temperature.

For the directed design of many of the functions in the electronic interface, accurate models for simulation are required. While significant work has been presented on DC characterization at cryogenic temperatures, comparatively little work covering low-frequency noise is available. To help further development, an extensive low-frequency noise characterization is performed on a 40nm CMOS technology at cryogenic temperature. The results of this characterization allow a broad overview over the low frequency noise behavior of the technology. Given the radical change in temperature between room-temperature and cryogenic temperature, a surprisingly small overall change in the input-referred noise is observed. The most prominent difference is the finding of a systematic Lorentzian feature at cryogenic temperature that is for the first time described here.

Lastly, while promising designs have been suggested for the DC-readout of spin qubits, guidelines for directing such designs have been lacking. In order to provide a set of such guidelines, we first demonstrate that the limits of DC-readout lie significantly beyond current state-of-the-art, with much room for improvement on the electronics. Then, we analyze the voltage amplifier, the transimpedance amplifier, the charge sampling, and the current pre-amplifier by deriving their design equations and trade-offs.
Finally the various architectures are compared with the fundamental limit and suggestions for specific use-cases are give. The results suggest that DC-readout is a promising path for the development of a scalable spin-qubit readout.@en

This article presents a two-times interleaved, loop-unrolled SAR analog-to-digital converter (ADC) operational from 300 down to 4.2 K. The 6-8-bit resolution and the sampling speed up to 1 GS/s are targeted at digitizing the multi-channel frequency-multiplexed input in a spin-qubit reflectometry readout for quantum computing. To optimize the circuit for the altered device behavior at cryogenic temperatures, a modified common-mode switching scheme is adopted as well as a flexible calibration. The design is implemented in 40-nm CMOS technology and achieves 36.2-dB signal to noise and distortion ratio (SNDR) for Nyquist input at 4.2 K while maintaining a Walden figure of merit (FOM textsubscript W) of 200 pJ/conv-step (for a 10.8-mW power consumption), including the clock receiver, and 15 pJ/conv-step (for a 0.8-mW power consumption) for just the core ADC. With these specifications, the ADC can support the simultaneous readout of 20 qubit channels with a power consumption of 0.5 mW/qubit, thus advancing toward the full integration of the cryogenic readout for future large-scale quantum processors.

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This paper presents a floating inverter amplifier (FIA) that performs high-linearity amplification and sampling while driving a 2<inline-formula> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> time-interleaved (TI) SAR ADC, operating from room temperature (RT) down to 4.2 K. The power-efficient FIA samples the continuous-time input signal by windowed integration, thus avoiding the traditional sample-and-hold. Cascode switching, a floating supply and accurate pulse-width timing calibration enable high-speed operation and interleaving. In addition, by exploiting the behavior of CMOS devices at cryogenic temperatures, forward-body-biasing (FBB) is pushed well beyond what is possible at RT to ensure performance down to 4.2 K, and its impact on the performance of cryogenic circuits is analyzed. The resulting ADC, implemented in 40-nm bulk CMOS and including the FIA driver, achieves SNDR<inline-formula> <tex-math notation="LaTeX">$=$</tex-math> </inline-formula>38.7 dB (38.2 dB), SFDR<inline-formula> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula>50 dB (<inline-formula> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula>50 dB), and FOMW<inline-formula> <tex-math notation="LaTeX">$=$</tex-math> </inline-formula>25.4 fJ/conv-step (31.3 fJ/conv-step) with Nyquist-rate input at 1.0 GS/s (0.9 GS/s) at 4.2 K (RT), respectively.

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This paper reports the experimental characterization and modelling of a stand-Alone StrongARM comparator at both room temperature (RT) and cryogenic temperature (4.2 K). The observed 6-dB improvement in the comparator input noise at 4.2 K is attributed to the reduction of the thermal noise and to the suppressed shot noise in the MOS transistors becoming dominant at cryogenic temperature. The proposed model is employed in the design of a loop-unrolled 2\times time-interleaved 1-GSa/s 7b SAR ADC for spin-qubit readout. As predicted by the comparator model, the ADC is noise-limited at RT to a SNDR of 38.2 dB at Nyquist input, while this improves to 41.1 dB at 4.2 K, now limited by distortion, thus resulting in the state-of-The-Art FoMw for cryo-CMOS ADC of 20.9 fJ/conv-step.

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Quantum computers (QCs) promise significant speedup for relevant computational problems that are intractable by classical computers. QCs process information stored in quantum bits (qubits) that must be typically cooled down to cryogenic temperatures. Since state-of-the-art QCs employ only a few qubits, those qubits can be driven and read out by room-temperature electronics connected to the cryogenic qubits by only a few wires. However, practical QCs will require more than thousands of qubits, making this approach impractical due to system complexity and reliability concerns. Although frequency multiplexing would reduce the interconnects to room temperature by fitting many qubit channels in the same physical interconnect, an excessive number of interconnects would still be required. An alternative, more scalable solution is a cryogenic electronic interface operating very close to the quantum processor to keep the whole control loop at cryogenic temperature, hence avoiding any high-speed interconnect to room temperature. This system must comprise drivers, readout circuits (LNAs, ADCs), and a digital controller to steer the quantum-algorithm execution [1]. While cryogenic CMOS (cryo-CMOS) wideband drivers and LNAs supporting qubit frequency multiplexing have been shown before [1] -[3], no wideband cryo-CMOS ADC has been demonstrated yet.

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CMOS circuits operating at cryogenic temperature (cryo-CMOS) are required in several lowerature applications. A compelling example is the electronic interface for quantum processors, which must reside very close to the cryogenic quantum devices it serves, and hence operate at the same temperature, so as to enable practical large-scale quantum computers. Such cryo-CMOS circuits must achieve extremely high performance while dissipating minimum power to be compatible with existing cryogenic refrigerators. These requirements asks for cryo-CMOS electronics on par with or even exceeding their roomerature counterparts. This paper overviews the challenges and the opportunities in designing cryo-CMOS circuits, with a focus on analog and mixed-signal circuits, such as voltage references and data converters.

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Accurate and low-noise generation and amplification of microwave signals are required for the manipulation and readout of quantum bits (qubits). A fault-tolerant quantum computer operates at deep cryogenic temperatures (i.e., <100 mK) and requires thousands of qubits for running practical quantum algorithms. Consequently, CMOS radio-frequency (RF) integrated circuits operating at cryogenic temperatures down to 4 K (Cryo-CMOS) offer a higher level of system integration and scalability for future quantum computers. In this paper, we extensively discuss the role, benefits, and constraints of Cryo-CMOS for qubits control and readout. The main characteristics of the CMOS transistors and their impacts on RF circuit designs are described. Furthermore, opportunities and challenges of low noise RF signal generation and amplification are investigated.

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