Quantum computers have gained widespread interest from both industry and academia in the last decade as they are very promising for solving problems intractable by classical computers. However, there is a limited number of qubits in current quantum processors, which impedes the practical applications of a quantum computer. To increase the number of qubits and scale up a quantum computer, a classical electronic interface is required to control and read out the quantum processor operating at cryogenic temperatures....@en

This article presents the first cryogenic phase-locked loop (PLL) operating at 4.2 K. The PLL is designed for the control system of scalable quantum computers. The specifications of PLL are derived from the required control fidelity for a single-qubit operation. By considering the benefits and challenges of cryogenic operation, a dedicated analog PLL structure is used so as to maintain high performance from 300 to 4.2 K. The PLL incorporates a dynamic-amplifier-based charge-domain sub-sampling phase detector (PD), which simultaneously achieves low phase noise (PN) and low reference spur, thanks to its high phase-detection gain and minimized periodic disturbances on the voltage-controlled oscillator (VCO) control. Fabricated in a 40-nm CMOS process, the PLL achieves <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>78.4-dBc reference spur, 75-fs rms jitter, and 4-mW power consumption at 300 K when generating a 10-GHz carrier, leading to a <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>256.5-dB jitter-power FOM. At 4.2 K, the PLL synthesizes 9.4-to 11.6-GHz tones with an rms jitter of 37 fs and a reference spur of <inline-formula> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula>69 dBc while consuming 2.7 mW at 10 GHz.

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This article presents a 4-to-5GHz LC oscillator operating at 4.2K for quantum computing applications. The phase noise (PN) specification of the oscillator is derived based on the control fidelity for a single-qubit operation. To reveal the substantial gap between the theoretical predictions and measurement results at cryogenic temperatures, a new PN expression for an oscillator is derived by considering the shot-noise effect. To reach the optimum performance of an LC oscillator, a common-mode (CM) resonance technique is implemented. Additionally, this work presents a digital calibration loop to adjust the CM frequency automatically at 4.2K, reducing the oscillator's PN and thus improving the control fidelity. The calibration technique reduces the flicker corner of the oscillator over a wide temperature range (10 $\times $ and 8 $\times $ reduction at 300K and 4.2K, respectively). At 4.2K, our 0.15-mm2 oscillator consumes a 5-mW power and achieves a PN of -153.8dBc/Hz at a 10MHz offset, corresponding to a 200-dB FOM. The calibration circuits consume only a 0.4-mW power and 0.01-mm2 area.

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This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing any power-hungry isolation buffers, the proposed phase detector dramatically suppresses the reference spurs by both minimizing the modulated capacitance seen by the voltage-controlled oscillator (VCO) tank and by reducing the duty cycle of the sampling clock. A 50μW RF-dividerless frequency-tracking loop is also introduced to lock the CSPLL robustly when the VCO faces a sudden frequency disturbance. Fabricated in a 40-nm CMOS process, the prototype CSPLL occupies a core area of 0.13 mm ² and synthesizes 9.6-to-12-GHz tones using a 100-MHz reference. At 11.2 GHz, it achieves a reference spur of −77.3 dBc and an RMS jitter of 48.6 fs while consuming 5 mW.

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LC VCOs with low phase noise (PN) and an octave frequency-tuning range (FTR) are required for multistandard communication devices, software-defined radios, and wireline data links. A viable popular approach is to exploit multicore mode-switching VCOs for two reasons: (1) their PN improves linearly by in-phase coupling of N identical VCOs; (2) the resonant-mode switching enhances the VCO FTR without degrading the tank quality factor (Q) as no RF current ideally flows through lossy mode-selection switches. However, it is still challenging for dual-mode VCOs to achieve a competitive FoM while covering an octave FTR at oscillation frequencies (F_OSC) above 6GHz [1]. To enhance the number of oscillation modes to 3, [2] added a center-loop inductor (L_C) to a transformer, as shown in Fig. 9.2.1. However, a large FTR gap is measured, since the transformer windings should be strongly coupled to accommodate L_C, The authors of [3] and [4] realized a triple- and quad-mode operation, respectively, by coupling two individual transformer-based resonators (see Fig. 9.2.1). Apart from the large area penalty, the former needs an extra third winding (L_T) in each transformer that degrades the tank Q, while the latter used large, fixed coupling capacitors (C_M) that load the tank in two of the resonant modes, thus limiting the VCO FTR.

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This paper presents a 15b cryo-CMOS DAC for multiplexed spin-qubit biasing implemented in a 22-nm FinFET process. The integrating-DAC architecture and the robust digitally-assisted high-voltage output stage enable a low power dissipation (157W) and small area (0.08mm2) independent of the number of biased qubits, and a 3V output range well beyond the nominal supply. This represents the first scalable solution for cryo-CMOS qubit biasing, which achieves a 1.8× better voltage resolution with a lower DNL over a 3× larger output range than the current state-of-the-art.

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In a fractional-N PLL, it is beneficial to minimize the input range of its phase detector (PD) as it promotes better linearity and higher PD gain for suppressing noise contributions of the following loop components. This can be done by canceling the predicted instantaneous time offset between the frequency reference (FREF) and the variable oscillator-clock (CKV) edges prior to the PD. There are currently two main cancellation strategies. The first is to align FREF and CKV by inserting a digital-to-time converter (DTC) on either path. However, due to the DTC nonlinearity and its susceptibility to PVT variations, the PLL can suffer from large fractional spurs. Although system-level techniques, e.g., background calibration [1], supply ripple reduction [2], and DTC code randomization [3], can partially alleviate these DTC issues, the overall system complexity worsens. The second method is to convert and cancel the predicted time offset in the voltage domain [4]. This arrangement is less sensitive to PVT variations. However, the accuracy of the time-to-voltage conversion relies on the strict trade-offs between the power consumption, noise, and linearity of a current source. In this work, we introduce a third solution based on a time-mode arithmetic unit (TAU), which outputs a weighted sum of time delays between the (falling) edges of FREF and CKV, as well as between two consecutive CKV edges. Compared with DTC-based solutions, it is less sensitive to PVT variations, as its output merely varies by the ratio of RC time constants, thus ensuring low fractional spurs with no extra system complexity. Compared to the voltage-domain solutions, the absence of a current source is beneficial for phase-noise optimization and migration to more advanced technology nodes. Moreover, TAU can implicitly provide a time-amplification (TA) gain, thus further suppressing the noise of subsequent blocks.@en

In this article, we present a 4.5-5.1-GHz fractional-N digitally intensive phase-locked loop (DPLL) capable of maintaining its performance in face of a large supply ripple, thus enabling a direct connection to a switched-mode dc-dc converter. Supply pushing of its inductor-capacitor (LC) oscillator is suppressed by properly replicating the supply ripple onto the gate of its tail current transistor, while the optimum replication gain is determined by a new on- chip calibration loop tolerant of supply variations. A proposed configuration of cascading a supply-insensitive slope generator with an output of a current digital-to-analog converter (DAC) linearly converts the phase error timing into a corresponding voltage, which is then quantized by a successive approximation register (SAR) analog-to-digital converter (ADC) to generate a digital phase error. We also introduce a low-power ripple pattern estimation and cancellation algorithm to remove the phase error component due to the supply-induced delay variations of loop components. Implemented in 40-nm CMOS, the DPLL prototype achieves the performance of 428-fs rms jitter, <-55-dBc fractional spur, and <-54-dBc maximum spur while consuming 3.25 mW and being subjugated to a sinusoidal or sawtooth supply ripple of 50 mVpp at 50-MHz reference divided by 3, 6, or 12.

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In quantum computing (QC) systems, cryogenic electronic interfaces can address the scalability and sheer interconnect complexity of the control/readout of thousands of quantum bits (qubits) required to execute practical quantum algorithms [1]. As shown in Fig.1-top, a frequency synthesizer is one of the main building blocks of such a cryogenic CMOS (cryo-CMOS) controller. However, designing a cryo-CMOS PLL for QC applications presents several challenges. Firstly, <60 fsec integrated jitter (σj) is required to achieve a single-qubit gate fidelity of 99.999% [2]. Secondly, to control multiple qubits with a single cable, a frequency multiplexed controller demands <-60dBc reference spur (SREF) to avoid interfering with other qubits. Thirdly, as the dilution fridge cooling power is limited, a low power consumption (PDC) is necessary to simultaneously control more qubits. Finally, PLL must be extremely robust against PVT variations, as it operates at a physical temperature of 4.2K, where no mature models are available. To address those issues, we report the first cryo-CMOS PLL operating at 4.2K. It achieves 45fsrms jitter and-71dBc SREF by introducing a charge-mode sub-sampling PLL that incorporates a new phase detector (PD) based on dynamic-amplifiers' operation.

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This paper presents a charge-sampling PLL (CSPLL), that demonstrates the best reported jitter-power FOM of-258.9 dB thanks to its high phase-detection gain and to the removal of the power-hungry buffer driving the phase detector. It also achieves-65 dBc of reference spur by both minimizing the modulated capacitance seen by the VCO tank and reducing the duty cycle of the sampling clock. Without requiring any RF dividers, a 50 μW frequency tracking loop is also introduced to robustly lock the CSPLL to a 100 MHz reference. Fabricated in 40-nm CMOS, the 0.13 mm2 CSPLL achieves an RMS jitter of 50 fsec at 11.4 GHz while consuming 5 mW.

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Low-power, low phase noise (PN) cryogenic frequency generation is required for the control electronics of quantum computers. To avoid limiting the performance of quantum bits, the frequency noise of a PLL should be < 1.9 kHz rms [1]. However, it is challenging for RF oscillators, as the heart of frequency synthesizers to satisfy such a requirement at cryogenic temperatures (CT), since 1) white noise in nanoscale CMOS devices is limited by temperature-independent shot noise; 2) the transistor 1/f noise is much higher, resulting in the oscillator PN being dominated by the 30dB/dec region [1].

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Accurate and low-noise generation and amplification of microwave signals are required for the manipulation and readout of quantum bits (qubits). A fault-tolerant quantum computer operates at deep cryogenic temperatures (i.e., <100 mK) and requires thousands of qubits for running practical quantum algorithms. Consequently, CMOS radio-frequency (RF) integrated circuits operating at cryogenic temperatures down to 4 K (Cryo-CMOS) offer a higher level of system integration and scalability for future quantum computers. In this paper, we extensively discuss the role, benefits, and constraints of Cryo-CMOS for qubits control and readout. The main characteristics of the CMOS transistors and their impacts on RF circuit designs are described. Furthermore, opportunities and challenges of low noise RF signal generation and amplification are investigated.

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