Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a ²⁸Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick ²⁸Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29 ± 0.02 μeV/Hz^½ at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to CZ-gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system.

Coherent links between qubits separated by tens of micrometers are expected to facilitate scalable quantum computing architectures for spin qubits in electrically defined quantum dots. These links create space for classical on-chip control electronics between qubit arrays, which can help to alleviate the so-called wiring bottleneck. A promising method of achieving coherent links between distant spin qubits consists of shuttling the spin through an array of quantum dots. Here, we use a linear array of four tunnel-coupled quantum dots in a 28Si/SiGe heterostructure to create a short quantum link. We move an electron spin through the quantum dot array by adjusting the electrochemical potential for each quantum dot sequentially. By pulsing the gates repeatedly, we shuttle an electron forward and backward through the array up to 250 times, which corresponds to a total distance of approximately 80μm. We make an estimate of the spin-flip probability per hop in these experiments and conclude that this is well below 0.01% per hop.

Semiconductor spin qubits have gained increasing attention as a possible platform to host a fault-tolerant quantum computer. First demonstrations of spin qubit arrays have been shown in a wide variety of semiconductor materials. The highest performance for spin qubit logic has been realized in silicon, but scaling silicon quantum dot arrays in two dimensions has proven to be challenging. By taking advantage of high-quality heterostructures and carefully designed gate patterns, we are able to form a tunnel coupled 2 × 2 quantum dot array in a ²⁸Si/SiGe heterostructure. We are able to load a single electron in all four quantum dots, thus reaching the (1,1,1,1) charge state. Furthermore, we characterize and control the tunnel coupling between all pairs of dots by measuring polarization lines over a wide range of barrier gate voltages. Tunnel couplings can be tuned from about 30 μ eV up to approximately 400 μ eV . These experiments provide insightful information on how to design 2D quantum dot arrays and constitute a first step toward the operation of spin qubits in ²⁸Si/SiGe quantum dots in two dimensions.

As spin-based quantum processors grow in size and complexity, maintaining high fidelities and minimizing crosstalk will be essential for the successful implementation of quantum algorithms and error-correction protocols. In particular, recent experiments have highlighted pernicious transient qubit frequency shifts associated with microwave qubit driving. Work-Arounds for small devices, including prepulsing with an off-resonant microwave burst to bring a device to a steady state, wait times prior to measurement, and qubit-specific calibrations all bode ill for device scalability. Here, we make substantial progress in understanding and overcoming this effect. We report a surprising nonmonotonic relation between mixing chamber temperature and spin Larmor frequency which is consistent with observed frequency shifts induced by microwave and baseband control signals. We find that purposefully operating the device at 200 mK greatly suppresses the adverse heating effect while not compromising qubit coherence or single-qubit fidelity benchmarks. Furthermore, systematic non-Markovian crosstalk is greatly reduced. Our results provide a straightforward means of improving the quality of multispin control while simplifying calibration procedures for future spin-based quantum processors.

Future quantum computers capable of solving relevant problems will require a large number of qubits that can be operated reliably1. However, the requirements of having a large qubit count and operating with high fidelity are typically conflicting. Spins in semiconductor quantum dots show long-term promise2,3 but demonstrations so far use between one and four qubits and typically optimize the fidelity of either single- or two-qubit operations, or initialization and readout4-11. Here, we increase the number of qubits and simultaneously achieve respectable fidelities for universal operation, state preparation and measurement. We design, fabricate and operate a six-qubit processor with a focus on careful Hamiltonian engineering, on a high level of abstraction to program the quantum circuits, and on efficient background calibration, all of which are essential to achieve high fidelities on this extended system. State preparation combines initialization by measurement and real-time feedback with quantum-non-demolition measurements. These advances will enable testing of increasingly meaningful quantum protocols and constitute a major stepping stone towards large-scale quantum computers.

As part of the National Agenda for Quantum Technology, QuTech (TU Delft and TNO) has agreed to make quantum technology accessible to society and industry via its full-stack prototype: Quantum Inspire. This system includes two different types of programmable quantum chips: circuits made from superconducting materials (transmons), and circuits made from silicon-based materials that localize and control single-electron spins (spin qubits). Silicon-based spin qubits are a natural match to the semiconductor manufacturing community, and several industrial fabrication facilities are already producing spin-qubit chips. Here, we discuss our latest results in spin-qubit technology and highlight where the semiconducting community has opportunities to drive the field forward. Specifically, developments in the following areas would enable fabrication of more powerful spin-qubit based quantum computing devices: circuit design rules implementing cryogenic device physics models, high-fidelity gate patterning of low resistance or superconducting metals, gate-oxide defect mitigation in relevant materials, silicon-germanium heterostructure optimization, and accurate magnetic field generation from on-chip micromagnets.

Full-scale quantum computers require the integration of millions of qubits, and the potential of using industrial semiconductor manufacturing to meet this need has driven the development of quantum computing in silicon quantum dots. However, fabrication has so far relied on electron-beam lithography and, with a few exceptions, conventional lift-off processes that suffer from low yield and poor uniformity. Here we report quantum dots that are hosted at a ²⁸Si/²⁸SiO₂ interface and fabricated in a 300 mm semiconductor manufacturing facility using all-optical lithography and fully industrial processing. With this approach, we achieve nanoscale gate patterns with excellent yield. In the multi-electron regime, the quantum dots allow good tunnel barrier control—a crucial feature for fault-tolerant two-qubit gates. Single-spin qubit operation using magnetic resonance in the few-electron regime reveals relaxation times of over 1 s at 1 T and coherence times of over 3 ms.

Solid-state qubits integrated on semiconductor substrates currently require at least one wire from every qubit to the control electronics, leading to a so-called wiring bottleneck for scaling. Demultiplexing via on-chip circuitry offers an effective strategy to overcome this bottleneck. In the case of gate-defined quantum dot arrays, specific static voltages need to be applied to many gates simultaneously to realize electron confinement. When a charge-locking structure is placed between the quantum device and the demultiplexer, the voltage can be maintained locally. In this study, we implement a switched-capacitor circuit for charge-locking and use it to float the plunger gate of a single quantum dot. Parallel plate capacitors, transistors, and quantum dot devices are monolithically fabricated on a Si/SiGe-based substrate to avoid complex off-chip routing. We experimentally study the effects of the capacitor and transistor size on the voltage accuracy of the floating node. Furthermore, we demonstrate that the electrochemical potential of the quantum dot can follow a 100 Hz pulse signal while the dot is partially floating, which is essential for applying this strategy in qubit experiments.

Electrons and holes confined in quantum dots define excellent building blocks for quantum emergence, simulation, and computation. Silicon and germanium are compatible with standard semiconductor manufacturing and contain stable isotopes with zero nuclear spin, thereby serving as excellent hosts for spins with long quantum coherence. Here, we demonstrate quantum dot arrays in a silicon metal-oxide-semiconductor (SiMOS), strained silicon (Si/SiGe), and strained germanium (Ge/SiGe). We fabricate using a multi-layer technique to achieve tightly confined quantum dots and compare integration processes. While SiMOS can benefit from a larger temperature budget and Ge/SiGe can make an Ohmic contact to metals, the overlapping gate structure to define the quantum dots can be based on a nearly identical integration. We realize charge sensing in each platform, for the first time in Ge/SiGe, and demonstrate fully functional linear and two-dimensional arrays where all quantum dots can be depleted to the last charge state. In Si/SiGe, we tune a quintuple quantum dot using the N + 1 method to simultaneously reach the few electron regime for each quantum dot. We compare capacitive crosstalk and find it to be the smallest in SiMOS, relevant for the tuning of quantum dot arrays. We put these results into perspective for quantum technology and identify industrial qubits, hybrid technology, automated tuning, and two-dimensional qubit arrays as four key trajectories that, when combined, enable fault-tolerant quantum computation.

We investigate the structural and quantum transport properties of isotopically enriched Si28/SiO228 stacks deposited on 300-mm Si wafers in an industrial CMOS fab. Highly uniform films are obtained with an isotopic purity greater than 99.92%. Hall-bar transistors with an oxide stack comprising 10 nm of Si28O2 and 17 nm of Al2O3 (equivalent oxide thickness of 17 nm) are fabricated in an academic cleanroom. A critical density for conduction of 1.75×1011cm-2 and a peak mobility of 9800cm2/Vs are measured at a temperature of 1.7 K. The Si28/SiO228 interface is characterized by a roughness of Δ=0.4nm and a correlation length of Λ=3.4nm. An upper bound for valley splitting energy of 480μeV is estimated at an effective electric field of 9.5 MV/m. These results support the use of wafer-scale Si28/SiO228 as a promising material platform to manufacture industrial spin qubits.