This paper presents a power- and area-efficient approach to digitizing the echo signals received by piezoelectric transducer elements, commonly used for ultrasound imaging. This technique utilizes such elements not only as sensors but also as the loop filter of an element-level δσ analog to digital converter (ADC). The receiver chain is thus greatly simplified, yielding savings in area and power. Every ADC becomes small enough to fit underneath a 150 μm × 150 μm transducer element, enabling simultaneous acquisition and digitization from all the elements in a 2-D array. This is especially valuable for miniature 3-D probes. Experimental results are reported for a prototype receiver chip with an array of 5×4 element-matched ADCs and a transducer array fabricated on top of the chip. Each ADC consumes 800 μW from a 1.8 V supply and achieves a SNR of 47 dB in a 75% bandwidth around a center frequency of 5 MHz.@en

This paper presents a power-and area-efficient front-end application-specific integrated circuit (ASIC) that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm² ASIC, implemented in a low-voltage 0.18-μm CMOS process, effectively reduces the number of receive (RX) cables required in the probe's narrow shaft by ninefold with the aid of 96 delay-and-sum beamformers, each of which locally combines the signals received by a sub-array of 3 × 3 elements. These beamformers are based on pipeline-operated analog sample-and-hold stages and employ a mismatch-scrambling technique to prevent the ripple signal associated with the mismatch between these stages from limiting the dynamic range. In addition, an ultralow-power low-noise amplifier architecture is proposed to increase the power efficiency of the RX circuitry. The ASIC has a compact element matched layout and consumes only 0.27 mW/channel while receiving, which is lower than the state-of-the-art circuit. Its functionality has been successfully demonstrated in 3-D imaging experiments.

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This work presents a compact ADC architecture capable of digitizing the signals received by every individual element of a 2D ultrasound transducer array. An element-matched layout of 150 μm × 150 μm is realized by exploiting each piezo-electric transducer element not only as the signal source, but also as the electro-mechanical loop-filter of a continuoustime band-pass ΔΣ ADC, thus minimizing the required circuit blocks. The transducer's frequency response, which is inherently matched with the signal bandwidth of interest, provides noise shaping to the ADC. A prototype chip has been fabricated in a 0.18 μm CMOS technology, featuring 20 ADCs located directly underneath a 150 μm-pitch piezo-electric transducer array fabricated on top of the chip. Each ADC, clocked at 200 MHz, consumes 800 μψ from a 1.8 V supply, and achieves an SNR of 47 dB in a 75% bandwidth around a center frequency of 5 MHz. Acoustic measurements show that the ADC successfully digitizes incoming echo signals.@en

This paper presents a power- and area-efficient front-end ASIC that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable the next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm2 ASIC, implemented in a low-voltage 0.18 μm CMOS process, effectively reduces the number of cables required in the probe's narrow shaft by means of 96 sub-array beamformers, which have a compact element-matched layout and employ mismatch-scrambling to enhance the dynamic range. The ASIC consumes less than 230 mW while receiving and its functionality has been successfully demonstrated in a 3-D imaging experiment.@en

This paper presents the design, fabrication, and experimental evaluation of a prototype lead zirconium titanate (PZT) matrix transducer with an integrated receive ASIC, as a proof of concept for a miniature three-dimensional (3-D) transesophageal echocardiography (TEE) probe. It consists of an array of 9 × 12 piezoelectric elements mounted on the ASIC via an integration scheme that involves direct electrical connections between a bond-pad array on the ASIC and the transducer elements. The ASIC addresses the critical challenge of reducing cable count, and includes front-end amplifiers with adjustable gains and microbeamformer circuits that locally process and combine echo signals received by the elements of each 3 × 3 subarray. Thus, an order-of-magnitude reduction in the number of receive channels is achieved. Dedicated circuit techniques are employed to meet the strict space and power constraints of TEE probes. The ASIC has been fabricated in a standard 0.18-μm CMOS process and consumes only 0.44 mW/channel. The prototype has been acoustically characterized in a water tank. The ASIC allows the array to be presteered across ±37° while achieving an overall dynamic range of 77 dB. Both the measured characteristics of the individual transducer elements and the performance of the ASIC are in good agreement with expectations, demonstrating the effectiveness of the proposed techniques.@en