The goal of this thesis is the design and development of the QuTech Central Controller, a system conceived to serve as the hardware/software interface of a quantum computer. This system represents an evolution of the QuMA microarchitecture to control a Surface-17 superconducting quantum processor, even though several architectural mechanisms are used to ensure the compatibility of the design with different quantum hardware technologies. In addition to an expansion of the control microarchitecture, the QuTech Central Controller represents an evolution of the overall system architecture, making use of a different hardware infrastructure to overcome previous scalability limitations.

The main contributions of this thesis are a proposed centralized microarchitecture capable of controlling up to 17 qubits, the implementation of this microarchitecture in a device called the QuTech Central Controller and its testing in dynamic quantum information processing experiments with superconducting qubits.

Over the course of the last decade, an interest has emerged in nearest neighbor constraints for quantum circuit design. The challenge herein is to bothminimize the running time of a circuit and tomodify it such that quantum gates only act on adjacent qubits while leaving the desired computational operation intact. These modifications involve the insertion of SWAP gates, which introduces computational overhead. Several exact and heuristic methods have been developed to determine the minimal number of required SWAP gates. Until now, the model sizes of exact methods scale superexponentionally in the number of qubits of the quantum circuit. The main research goal of this project was to develop an integer linear program that instead scales polynomially both in the number of qubits and the number of quantum gates in the quantumcircuit. 7 First, qubits located on a linear array were considered. The resulting integer linear program proposed requires O(n^2 m) variables and constraints, where n denotes the number of qubits and m denotes the number of quantum gates of the quantum circuit under consideration. Second, qubits located on a two- or threedimensional grid were considered. The programs both require O(n4m) variables and O(n^3 m) constraints. Subsequently we prove that, for a fixed quantum circuit, the optimal objective value of the one-dimensional problem is an upper bound for the optimal objective value of the corresponding two- and three-dimensional problems. Using CPLEX’s Branch & Bound method, 131 benchmark instances of various circuit sizes were evaluated. The largest of which contained either eighteen qubits and sixteen quantum gates, or five qubits and 112 quantumgates. Furthermore, we identify problems on the interface of nearest neighbor compliant quantum circuit design and distributed quantum computing. Integer linear program formulations are provided for these additional problems.

Fast sequencing and analysis of (microorganism, plant or human) genomes will open up new vistas in fields like personalised medication, food yield and epigenetic research. Current state-of-the-art DNA pattern matching techniques use heuristic algorithms on computing clusters of CPUs, GPUs and FPGAs. With genomic data set to eclipse social and astronomical big data streams within a decade, the alternate computing paradigm of quantum computation is explored to accelerate genome-sequence reconstruction. The inherent parallelism of quantum superposition of states is harnessed to design a quantum kernel for accelerating the search process. The project explores the merger of these two domains and identifies ways to fit these together to design a genome-sequence analysis pipeline with quantum algorithmic speedup. The design of a genome-sequence analysis pipeline with a quantum kernel is tested with a proof-of-concept demonstration using a quantum simulator.

If a practical quantum computer is to be built, it will not only need quantum programming languages and qubits, but hardware-software interfaces as well. These interfaces, also known as computer (micro)architectures are the key to creating a ’quantum stack’, where a programmer can directly execute programs onto quantum hardware. A functional quantum computer microarchitecture, the Central Controller-Light (CCLight), has been designed, implemented on a Field Programmable Gate Array (FPGA), and verified to control superconducting qubits successfully. The next logical step, in hopes of creating a more scalable quantum computing system, is to take the CCLight and implement it as an Application-Specific Integrated Circuit (ASIC). In this thesis, the CCLight was built into an ASIC. It was shown that this approach yields the potential for higher performance and lower power for the microarchitecture core, and the groundwork for more robust and automatic testing of similar microarchitectures was laid out. Lastly, the lack of scalability in the original approach, wherein the processor transmits multi-byte codewords to the analog/RF hardware controlling the qubits, was revealed.

Building a working quantum computer brings many challenges to overcome. For quanum processors, promising qubits seem to be NV-centres in diamond. Such processor is divided into processing units (PUs), each comprising an NV-centre with several carbon spin qubits, and they are interconnected with each other by optical links. The qubits within a PU can be modelled as nodes in a star graph and the optical connections as connections between the centres of the star graphs, such that the centres with their interconnections form a complete graph. We call the overall graph a fully connected star graph. In order to execute a quantum circuit, multiple pairs of qubits should be brought together in PUs at different times, which requires planning. Sorting the qubits is done via swaps. A swap within a PU can be performed easily, however, swapping between different PUs is done by teleportation, which is much more costly. Therefore, we neglect the costs of swaps within PUs. Parallellisation of swaps between PUs is done in a step. The less steps are used, the faster the quantum circuit is executed. In practice, as we are interested in fast computations, we often want to minimize the number of steps. The following problem is addressed. Given a current distribution of the qubits over the nodes in the fully connected star graph, and given a wanted, permuted distribution, minimize the number of swaps and/or steps to route the qubits from the current to the wanted distribution. At the moment, no efficient algorithm exists to sort the qubits especially in fully connected star graphs. Efficient solutions are presented in the form of algorithms. It is shown that qubit moves in fully connected star graphs can be scheduled efficiently, such that the number of moves is minimized. Guide lines are given to minimize the execution time too.