Keyword spotting (KWS) is an essential component of voice recognition services on smart devices. Its always-on characteristic requires high accuracy and real-time response. Also, low power consumption is another key demand for KWS devices. In previous research, neural networks have become popular for KWS tasks for their accuracy compared to traditional machine learning technologies. Among classical neural networks like recurrent neural networks (RNNs) and convolutional neural networks (CNNs), temporal convolutional networks (TCNs) have begun to catch attention recently. Moreover, studies related to sparsity are always an efficient method to deal with the growing model size issue for modern neural network designs. As a potential solution, in this work, a TCN model is trained for KWS on the Google Speech Command V2 dataset and achieves an accuracy of 94.1\%. Based on that, two different sparsity are applied to the TCN model. One is temporal sparsity. By creating a Delta convolution layer, the Delta temporal convolutional network (DeltaTCN) achieves an accuracy of 93.6\% with a 72\% reduction in floating-point operations (FLOPS) compared to the original TCN model. Another is structural weight sparsity. By creating sparsity on the weight matrix of each convolution layer, the structural sparse temporal convolutional network (SSPTCN) achieves 93.6\% accuracy with a 70\% reduction in FLOPs and a 39\% reduction in parameters.

Bidirectional neural recording ICs faces the challenge of simultaneous stimulation and recording. The recording IC should endure large stimulation artifacts while capturing weak neural signals excited by the stimuli. The stimulation artifacts can be as large as hundreds of millivolts, which can saturate the recording front end. Conventional neural-recording ICs use a low-noise-amplifier (LNA), a programmable-gain amplifier (PGA) followed by an analog-to-digital converter (ADC), leading to low power consumptions and great noise performances. However, the dynamic range (DR) is usually limited to 50 dB. State-of-the-art recording ICs using direct-conversion ADCs have been intro- duced to increase the DR. However, the typical power and area consumption for these architectures are exceeding the requirements for next-generation brain-computer interfaces. This work proposes a novel neural-recording IC system architecture with satu- ration prevention in presence of large stimulation artifacts. The proposed architecture consists of an AC-coupled boxcar sampler, switched-capacitor low-pass filter followed by a 10-bit asynchronous SAR ADC. The integrated voltage at the output of the boxcar sampler is sampled by the ADC and monitored by a level-cross detection block. Based on the output of the level-cross detection block, the integration time, and thus the gain, can be tuned to different configurations pre-defined in a look-up table (LUT). The additional noise penalty due to noise-folding from decreasing the integration time is compensated by oversampling and averaging. The proposed system architecture is partially imple- mented at transistor level while the ADC and digital blocks are modeled using verilog-A as a proof-of-concept. The analog front-end achieves a DR of 69.5 dB with a peak-to-peak maximum input amplitude of 180 mVPP and a typical ENOB of 8.01 bits.

This work proposes an energy harvesting DC-DC converter that is able to efficiently process a wide input power range from 25 mW up to 250 mW, to charge a storage device used in Internet-of-Things (IoT) applications. An interleaved boost-converter topology with two inductors is used to divide the high currents over the two branches, in order to reduce the conduction losses in the MOSFET power switches at high input power.

A Maximum Power Point Tracking (MPPT) strategy is employed to find the optimal matching between the harvesting sensor, which in this case is a solar cell, and the input of the converter. The Maximum Power Point (MPP) is found by measuring the output current of the converter, decreasing the duty cycle of the switching power MOSFETs, and again measuring the output current to check if it increases. This process is repeated until the output current no longer increases, which is where the MPP will be. The duty-cycle pulses that control the power switches are generated by comparing a reference voltage representing the duty cycle with two sawtooth waves with a phase difference of 180 degrees generated on-chip.

Usually, for converters that handle large currents, large power switches are required to keep the on-resistance of the switches minimal such that the conduction losses do not dominate. Since the converter also needs to be able to efficiently convert smaller powers, the size of the power switches is made configurable. This is necessary since otherwise the gate-charge losses will become dominant. The total size of the segmented power switches are controlled digitally by a logic unit that calculates the expected input current using 2-bit representations of the measured output current and the two most significant bits of the 5-bit representation for the duty cycle set by the MPPT.

Schematic simulation results show a conversion efficiency of up to 92%. The proposed system is designed and simulated using 180 nm TSMC CMOS technology. The chip covers a total silicon area of 2.20 mm2, with an active area of 1.12 mm2.

Time-of-Flight (ToF) is an optical range detection technique that derives range from the round-trip time of light pulse between the imager and the target. Due to the simple hardware and distance extraction algorithm, ToF imagers are widely adopted in existing (automotive, consumer electronics, etc.) and emerging (AR/VR, etc.) applications requiring depth information. ToF is divided into Direct-ToF (D-ToF) and Indirect-ToF (I-ToF). Compared with the D-ToF system which directly measures the round-trip time of the laser beam, the I-ToF system indirectly measures the time from a phase measurement of the received modulated pulse. I-ToF provides a smaller detection range but it is less sensitive to jitter in the system and can achieve higher accuracy. Hence, I-ToF is used in short-range high precision applications such as face recognition.

This thesis describes the readout ADC design for the next-generation I-ToF imagers used for smartphone face recognition in collaboration with Infineon. A compact 11-bit 2 MS/s column-level ADC is developed in 65nm CMOS image technology. To balance between the available area and required speed, a hybrid SAR-RAMP ADC concept is proposed, which also embeds a threshold comparison phase to relax requirements on successive phases. The ADC has been verified with the post-layout extracted view of the column-level analog circuits and the schematic view of the central/digital circuits with an ideal ramp buffer, achieving a 1.1 V - 3.3 V input range with a 1.1 V reference, a signal-to-noise and distortion ratio (SNDR) of 64.3 dB, 45 µW power consumption, a Walden figure of merit (FOM$_W$) of 107 fJ/conv-step and an area of 7 µm $\times$ 815 µm.

This work proposes an energy harvesting platform that is able to convert power from both DC sources (photo-voltaic cells and TEGs) as well as piezo element sources. It does so only using a single input channel to which a single harvester can be connected. The proposed system is able to differentiate between the two source types and adjust the power converter configuration accordingly.For the DC sources, a novel switched-capacitor power converter (SCPC) is proposed, that is able to convert the energy from a harvester that has a maximum power point (MPP) output voltage of 170mV to 5V and a maximum power point output power of 10uW to 50mW. This DC-DC converter offers 119 different positive voltage conversion ratios, with a maximum voltage conversion ratio of 16, using four in-package capacitors. As a result of this high number of conversion ratios, the MPP output voltage of the harvester and the input voltage of the power converter are matched accurately, causing the harvesting efficiency to be very high. A maximum harvesting efficiency of 96.2% is found in simulations. For the piezo element sources, the concept of a flipping-capacitor rectifier (FCR) has been adjusted to work in harmony with the designed SCPC. In a steady-state condition, the capacitors of the SCPC reach specific voltages, such that they can create evenly spaced voltage steps for the flipping operation. With this technique, a voltage flipping efficiency of 0.9375 and a theoretical maximum output power improvement rate (MOPIR) of 32 can be reached. Due to losses in the system, simulation results show a MOPIR of up to 20.0, which is still significantly higher than the state-of-art. The system is designed to work with harvesters with a piezo capacitance of up to 100nF, an excitation frequency of 1Hz to 200Hz and an equivalent FBR maximum power point output power of 1uW to 50mW. An implementation of the proposed system is discussed and simulated. The total active silicon area for the designed system is 2.12mm2 in a 0.18 um TSMC technology.