A triboelectric nanogenerator (TENG) is a kinetic energy transducer with small and time-varying internal capacitance, which increases the difficulties of extracting harvested energy. In this paper, an efficient rectifier, hybridizing synchronized electric charge extraction (SECE) and bias-flipping techniques, is proposed. The two techniques alternatively operate at opposite voltage polarities of the TENG. By taking advantage of the varying capacitance, the proposed synchronized extraction and flipping (SEF) rectifier shows significantly improved energy extraction performance. The design is implemented in a 180-nm high-voltage BCD technology, and the results show a 7.4X energy extraction enhancement, 65-V voltage tolerance, and 35-nA quiescent current.

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Multiple parameter environment monitoring via wireless Internet of Thing sensors is growing rapidly, thanks to low power techniques of the node. More importantly, the ever more complex and highly efficient energy harvesting systems enable long-term continuous monitoring in inaccessible environments without needing to change the battery. This paper reviews existing energy harvesting modalities, including photovoltaic, piezoelectric, pyroelectric, electromagnetic, and vibration, together with circuit techniques of interfacing power management circuits for energy harvesters. Moreover, techniques used to interface with multiple mode energy harvesters to obtain a stable output power with optimal power efficiency are discussed as an emerging direction. The state-of-the-art energy harvesting systems together with future development trends are provided.

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This article proposes a novel collaborative-flip synchronized switch harvesting on capacitors (CF-SSHCs) rectifier and multioutput synchronous dc-dc converters with shared capacitors. Compared to the traditional SSHC, our CF-SSHC rectifier can increase the number of flipping phases, potentially enhancing the flipping efficiency and output power under specific conditions where C FLY is close to C_P. The synchronous dc-dc converters reuse the flying capacitors to achieve a high maximum output power improving rate (MOPIR) over a limited input power range and provide multiple outputs. This work achieves an advanced number of flipping phases in capacitor-based rectifier interface technology and explores multiple-input multiple-output configurations, evaluating the system's performance under periodic and shock conditions for the first time. The system's adaptability to various piezoelectric transducer (PT) array configurations is validated, highlighting its potential for Internet of Things (IoT) networks. The design is fabricated in standard 0.18- μ m CMOS. Measurement results demonstrate that the voltage flipping efficiency of up to 83% is achieved. Compared with full-bridge rectifier (FBR), the MOPIR can be increased to 5.06 × and 4.78 × under off-resonance and on-resonance excitation, respectively. It can also achieve a 2.14 × power enhancement under shock excitation. Additionally, when the input power P INFBR is in the range of 1.42-28.4 μ W, the MOPIR of the proposed system is always greater than 4.

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The various application scenarios of triboelectric nanogenerator (TENG) have attracted increasing research interest, while one of the biggest challenges is the energy extraction efficiency. Due to the small and time-varying inherent capacitor in a TENG, the previous energy extraction techniques e.g., full-bridge rectifier (FBR) and bias-flip (BF) rectifier, performed not well. To extract more energy from TENG, this article proposed a fully integrated switched-capacitor (SC) rectifier with an electrostatic charge boosting (ECB) technique, achieving simultaneous extraction from the synchronized triboelectric energy and self-excited electrostatic energy. The proposed rectifier was fabricated in a 180-nm BCD process. With the proposed ECB technique, the theoretical analysis and measurements show a quadratically increasing output power with respect to the rectification voltage, attaining a constant maximum power point (MPP) at the breakdown voltage of the circuit. A maximum output power of 127.6 μ W is measured with a TENG fabricated in-house. Compared to a passive FBR, the proposed rectifier enhances the output power by 14 times.

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The growing trend of the Internet of Things (IoT) involves trillions of sensors in various applications. An extensive array of parameters need to be gathered concurrently with high-precision, low-cost, and low-power sensor nodes, such as resistive (R) and capacitive (C) sensors. Single-chip channel fusion can be an effective solution, while it is challenging to suppress the noise and integrate massive I/O pads. However, conventional oversampling noise-shaping methods increase power consumption, which fails to meet the demand of long-term monitoring applications. In addition, existing R/C sensor-interface chips require a pair of I/O pads for each sensor, where the pad frame dominates the overall chip area in massive-channel integration. In this work, we demonstrate a 72-channel R&C sensor-interface chip for proximity-and-temperature sensing. A noise-orthogonalizing technique is proposed to eliminate the quantization noise at the signal frequencies, achieving an energy efficiency of 19.1 pJ/step/channel. Moreover, a pad-sharing technique is proposed to reduce the number of I/O pads by half, enabling 72 sensors to be read by 36 pairs of I/O pads. The chip is fabricated by 65-nm CMOS technology, and measurement results show resolutions of 286 Omega and 162 fF, respectively. The power consumption and die area are reduced to 0.74 mu text{W} /Channel and 0.038 mm2/Channel, respectively.

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Synchronized rectifiers offer promising solutions for piezoelectric energy harvesting; however, achieving the promised energy extraction performance necessitates using either a bulky inductor or multiple large capacitors, which cannot be on-chip integrated and increase the system form factor. This article introduces a fully integrated sequenced synchronized switch harvesting on capacitors (3SHC) rectifier. The input piezoelectric transducer (PT) uses microelectromechanical system technology. The cantilever is equally split into multiple strongly coupled subcantilevers, with each cantilever treated as an individual PT connected to the proposed rectifier. The 3SHC rectifier cyclically operates multiple times to synchronously flip the voltage of each cantilever sequentially. With the proposed design, all the flying capacitors only need to match the capacitance of each subcantilever; hence, they can be fully integrated on-chip. The design is fabricated using standard 0.18 μ m CMOS technology. Measurement results show that the proposed 3SHC rectifier attains an 80% voltage flip efficiency and achieves a 730% power enhancement compared to a full-bridge rectifier.

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When driving a GaN switch, the maximum transition speed of drain-source voltage (peak dv/dt) should meet specification. But reducing the peak dv/dt usually exacerbates V-I overlap loss. This work presents a GaN driver for buck converter featuring: 1) voltage-controlled peak dv/dt; 2) almost constant dv/dt during Miller Plateau (MP) for reducing V-I overlap loss. We analyze why a constant dv/dt minimizes V-I overlap loss under a peak dv/dt specification, how to maintain a constant dv/dt during the MP period, and propose an implementable solution. We use a sensing block to judge whether the peak dv/dt violates the specification, and an adaptive searching scheme to find out the key parameters for the targeted constant dv/dt. We designed the layout with a 180-nm SOI process, and simulation results show that the peak dv/dt is well under control. It saves up to 33.99% V-I overlap loss when compared with the conventional constant current driver scheme.

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Body Channel Communication (BCC) utilizes the body surface as a low-loss signal transmission medium, reducing the power consumption of wireless wearable devices. However, the effective communication range on the human body is limited in the state-of-the-art BCC transceivers, where the signal loss between the body surface and the BCC receiver remains one of the main bottlenecks. To reduce the interface loss, a high input impedance is desired by the BCC receiver, but the DC-biasing circuits decrease the input impedance. In this work, a dynamically-sampling IFE is proposed to eliminate the DC voltage bias, resulting in a 90kΩ; high input impedance and a 94dB RF—IF conversion gain to reduce the interface loss in long-range BCC applications. The BCC transceiver chip is fabricated in 55nm CMOS process, taking a die area of 0.123mm². Measured results show that the chip extends the BCC range to 2m for both the forward and backward paths, where the transmitter and receiver consume 711μW power in total.

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This article presents a 13.56-MHz wireless power transfer (WPT) system with coupling variation robustness and high efficiency for powering biomedical implantable devices (IMDs). To sustain reliable power transfer against inductive-link fluctuation, a hybrid voltage-/current-mode (V/CM) receiver (RX) is proposed to provide CM recovery when the coupling becomes weak for VM operation. To optimize the end-to-end (E2E) efficiency, a digital pulsewidth modulation (PWM)-based global power regulation technique is proposed, which allows a fully on/off operation of the three-mode power amplifier (PA) at the transmitter (TX) side and fast load-transient responses. Moreover, the system adopts a fully integrated voltage-sensing load-shift-keying (LSK) demodulation technique, which replaces conventional current sensing methods with a streamlined implementation and reduced power consumption. Both prototype TX and RX chips were fabricated in a 180-nm CMOS process. The proposed system, powered by a 1.8-V supply at TX, realizes a regulated 1.8-V dc output at RX. With the help of the hybrid V/CM RX, the proposed system achieves an up-to-150% WPT range extension compared to VM-only operation and an up to 7.2-cm WPT range. Benefiting from the global digital-PWM regulation, it achieves up to 72.3% E2E efficiency over the loading range from 0.18 to 81 mW. A 10- μ s load-transient recovery is also attained at a 164 × load step with a 110-mV undershoot and unnoticeable overshoots.

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This article presents a 10mV-startup-voltage thermoelectric energy harvesting system, assisted by a piezoelectric generator (PEG) as a cold starter. It exploits the fact that when a thermoelectric energy harvesting system is implemented in a place where kinetic energy is also present, the PEG starter can provide a clock signal to start the system. Thanks to the high output impedance of the PEG, the generated clock voltage can easily go over several hundreds of mV, which can be used to drive the boost converter to harvest thermoelectric energy even at an extremely low thermoelectric generator (TEG) voltage. The proposed system was fabricated in a 180-nm BCD process. The measurement results show that the TEG system can start up from the cold state with a TEG voltage as low as 10 mV while maintaining a 63.9% efficiency. The peak power conversion efficiency reaches 83.7% when the TEG voltage is 55 mV.@en

Bias-flip rectifiers are commonly employed for piezoelectric energy harvesting (PEH). This article proposes a synchronized switch harvesting on an inductor (SSHI) rectifier with a duty-cycle-based (DCB) maximum power point tracking (MPPT) algorithm. The proposed DCB MPPT algorithm is based on the mathematically derived relation between the MPPT efficiency and the duty cycle of the bridge rectifier. The resulting equation shows that the MPPT efficiency only depends on the rectifier duty cycle, and is independent of any other system variables, such as voltage bias-flipping efficiency, the open-circuit voltage from the harvester, vibration frequency, etc. As a result, MPPT can be achieved by regulating the duty cycle, simplifying circuit implementation, and achieving self-regulating and continuous MPPT. This design was fabricated in a 180-nm BCD process. The measured results show 98% peak MPPT efficiency and up to 738% output power enhancement.

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A single-stage dual-output regulating voltage doubler (DOVD) is proposed for biomedical wireless power transfer (WPT) systems. Derived from the full-wave voltage doubler (VD) topology, it achieves ac-to-dc rectification and dual-output voltage regulation in a single stage by using only two power transistors. The DOVD's inherent voltage conversion ratio (VCR) of 2 enhances the overall voltage gain of a WPT system, thus extending the transfer range against varying link conditions. To eliminate cross-regulation between the two outputs and provide fast load-transient responses, a parallel pulse-frequency modulation (PPFM) controller is proposed. In addition, a digital-tuning adaptive delay compensation technique with fast error-variation responses is proposed to achieve soft-switching in the power stage. Implemented in a 180-nm Bipolar-CMOS-DMOS (BCD) technology and operating at 6.78 MHz, the proposed DOVD achieves dual regulated outputs at 1.8 and 3.3 V, a VCR of up to 1.875, and a power conversion efficiency (PCE) of up to 92.95% over an output power range of 2.6-90.5 mW. It also achieves instant load-transient responses and unnoticeable cross-regulation during 25× load transients at both outputs.

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This article presents a piezoelectric energy harvesting (PEH) interface circuit using a new self-bias-flip with the charge recycle (SBFR) technique without employing any additional energy reservoir. Traditional designs, including synchronous-switch harvesting on inductor (SSHI), synchronous-switch harvesting on capacitor (SSHC), synchronous electric charge extraction (SECE), etc., require additional capacitors or inductors to reverse the voltage on the PEH at the zero-crossing point. This design innovatively uses the inherent capacitors of the piezoelectric harvesters as the flipping capacitors. In order to improve the extract efficiency of the interface, the zero-crossing state is split into a charge recycle stage and a voltage-flip stage. For a piezoelectric array with 2^n PEHs, a configuration with (n-1) phases in the charge recycle stage is adopted to reduce the loss caused by direct charge neutralization. The charge redistribution loss is reduced by employing (2n+1) phases in the voltage-flip stage. The proposed principle has been implemented with discrete components and is verified by three different prototypes. The measurement results show that a flipping efficiency of 67% is achieved by utilizing SBFR with four PEHs. And the proposed interface can provide up to 5.2x improvement when compared with the full-bridge rectifier (FBR).

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In this letter, a 6.78-MHz single-stage regulating voltage-doubling rectifier is presented for biomedical wireless power transfer (WPT) applications. Derived from a full-wave voltage doubler, a theoretical voltage conversion ratio (VCR) of 2 can be achieved, which benefits the end-to-end voltage gain of a biomedical WPT system with varying link conditions. As a result, a wider WPT operational range and less coil-link loss can be achieved. To avoid efficiency loss due to cascading, the rectifier output is in-situ regulated in a sub-50-mV hysteresis window by pulse-skipping control. To ensure a high power conversion efficiency (PCE), adaptive delay-compensated active diodes are adopted with an offset locking technique. The input/output capacitors of the rectifier are fabricated on-chip, achieving a fully integrated design. The rectifier was fabricated in a 180-nm BCD process, occupying a silicon area of 0.3/2.7 mm2 without/with on-chip capacitors. The measurements show that the rectifier can realize a peak PCE at 90.6% when the output power is 79.8 mW. The PCE and VCR are achieved higher than 86.4% and 1.6, respectively, over a large loading range (from 1 to 40 mA). The rectifier can output a maximum power of 159.2 mW, satisfying most biomedical implants.

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With the advent of the lnternet-of-Things (1oT) era, sensor nodes are required in almost all fields to achieve a better interaction between humans and the environment. Piezoelectric energy harvester (PEH), which exhibits an equivalent electrical model of an AC current source /P in parallel with the inherent capacitor CP, is a promising technology to resolve the energy problem of such sensor nodes. Recently, inductor-based rectifiers, capacitor-based rectifiers and hybrid rectifiers have been proposed to improve the energy extraction efficiency of PEH devices [1]–[5]. However, these structures all require the aid of additional capacitors or inductors to achieve bias-flip operation, as illustrated in Fig. 1. These extra passive devices are typically large, which can be a major bottleneck in system-volumeconstrained applications such as MEMS [4]. In response to the above problem, this work proposes a novel 8-phase self bias-flip PEH interface with charge recycling and reusing (SBFRR). By using the C P of 4 PEHs as flipping capacitors, this scheme achieves a high voltage flipping efficiency without using extra energy reservoirs. The 4 C P can also serve as flying capacitors to achieve switched-PEH DC-DC (SPDC) conversion for MPPT, while maintaining a MOPIR of >3.5× with a PEH input voltage (Vp) from 0. 78Vto4.9V.@en

Synchronized ac-dc rectifiers are widely used for energy rectification in piezoelectric energy harvesting (PEH), which have to employ a bulky inductor or some dedicated flying capacitors for high energy conversion efficiency. This article proposes a synchronized switch harvesting on shared capacitors (SSHSC) rectifier achieving synchronized voltage flipping without inductors or dedicated flying capacitors for PEH. The proposed SSHSC rectifier employs only three energy-storage capacitors with a specific capacitance ratio (3:3:1). These three capacitors mainly serve as storage capacitors; they can also be reused as flying capacitors for bias-flip operations. Thanks to the capacitor-sharing technique, this SSHSC rectifier takes a small volume and fewer I/O pads compared to prior SSHC rectifiers. This design was fabricated in a 180-nm BCD process, and the measured results show 78% voltage flipping efficiency and 7.58 × power enhancement.

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This article proposes a novel eight-phase self-bias-flip piezoelectric energy harvesting interface with charge recycling and reusing (SBFRR) and a switched-piezoelectric energy harvester (PEH) dc–dc (SPDC) converter. The proposed scheme innovatively utilizes the inherent capacitors ( CP ) of four PEHs as energy sources, flying capacitors, and flipping capacitors for time-sharing reuse to achieve both a high-voltage flipping and dc–dc conversion efficiency, while avoiding the use of extra energy reservoirs. The design is fully integrated and fabricated in standard 0.18- μ m CMOS. Measurement result demonstrates that the voltage flipping efficiency of up to 80% is achieved. Compared with the ideal full-bridge rectifier (FBR), the measured maximum output power improving rate (MOPIR) can be increased to 4.88 × . In addition, with the four CP serving as flying capacitors to achieve SPDC conversion for maximum power point track (MPPT), an MOPIR of > 3.5 × can be maintained with a PEH input voltage from 0.78 to 4.9 V.

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A triboelectric nanogenerator (TENG) is a new transducer utilizing contact electrification and electrostatic induction to transform mechanical energy into electric energy. Due to its high energy density and flexibility, it can be employed to make electronic devices self-powered by harvesting ambient mechanical energy in many application scenarios, such as biomedical devices, wearable electronics, and Internet-of-Things (IoT) sensors. However, due to the time-varying and low internal capacitance of a TENG, it is challenging to extract electrical energy from it. Hence, good power conversion techniques are crucial in TENG energy harvesting systems. Currently, studies on dedicated integrated power conversion techniques are very limited. Due to the exponentially increasing research interests in TENG, a comprehensive study on the TENG energy harvesting system, emphasizing integrated-circuit (IC) power conversion techniques, is urgently needed. This paper summarizes and compares the state-of-the-art triboelectric energy harvesting systems, focusing on different power conversion techniques for output power enhancement. Some techniques, which have been widely used in other relevant energy harvesting systems, are also mentioned to inspire innovative design strategies for TENG systems.

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High-frequency buck converters need a fast transition of switching nodes (high dv/dt). Such high dv/dt, especially the positive one, can cause malfunction of a conventional pulse-triggered active-coupled (PTAC) level shifter that is used to control the high-side NMOS switch. In this work, we first discuss the dv/dt immunity of conventional PTAC level shifters. Subsequently, we propose a new scheme to block the noise current during the dv/dt sequence, allowing an almost full immunity to the positive dv/dt. With this scheme, the maximum dv/dt is determined by how well the circuitry is protected from the overvoltage during the dv/dt sequence. We design a 20-V buck converter with this level shifter, fabricated in 180-nm BCD process. Experimental results show it works correctly under a 67-V/ns dv/dt.@en

Synchronized bias-flip rectifiers, such as synchronized switch harvesting on inductor (SSHI) rectifiers, are widely used for piezoelectric energy harvesting (PEH) [1], which can replace the use of batteries in many loT applications, thus reducing both system volume and maintenance cost. However, the output power extracted by such rectifiers strongly depends on the impedance matching between the piezoelectric transducer (PT) and the circuit. To maximize this, two maximum power point tracking (MPPT) algorithms are often used. As shown in Fig. 30.3.1 (left), the Perturb & Observe (P&O) (a.k.a. hill-climbing) algorithm adjusts the rectified output power in a stepwise manner towards the maximum power point (MPP), thus establishing robust and continuous MPPT. However, accurately sensing the rectified output power often requires complex and power-hungry hardware [1], [2]. Another simpler algorithm is based on the fractional open-circuit voltage (FOCV) and involves periodically measuring the PT's open-circuit voltage amplitude (VOC) and regulating the rectified voltage (VREC) to a level (VMPP), which corresponds to the MPP [3-6]. However, the PT must be periodically disconnected from the rectifier to measure VOC, resulting in wasted energy, while the inherent delay in sensing VOC variations reduces the overall tracking efficiency. Furthermore, a calibration step is usually necessary to determine VMPP, since this depends on the actual PT voltage flip efficiency (etaF) of the bias-flip rectifier.

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