Body Channel Communication (BCC) offers a low-loss signal transmission medium for ultra-low-power wearable devices on human body [1]. However, the effective communication range on human body is limited to less than 1m in the state-of-the-art BCC transceivers [2], where the signal loss at the interface of body surface and BCC receiver remains to be one of the main bottlenecks. The limited communication range has blocked the popularization in many WBAN applications, such as signal transmission from to an intelligent insole to smart watch [3]. Relative to the high impedance of human body [4], the lower input impedance of BCC receiver induces significant signal loss. To reduce the interface loss, conventional interface front end (IFE) of BCC receivers was designed to be with a high input impedance [5], but the DC voltage bias decreased both the input impedance and signal gain of IFE.@en

The size of wireless systems is required to be reduced in many applications, such as ultra-low-power sensor nodes and wearable/implantable devices, where battery and crystal are the two main bottlenecks in system miniaturization. In recent years, battery-free radios based on wireless power transfer (WPT) have shown great potential in miniature wireless systems, while a reliable on-chip clock without a crystal remains a design challenge. Conventional methods utilized the RF WPT tone as the reference for clock generation, but the high RF frequency leads to high power consumption. In comparison, using a lower WPT frequency results in an antenna with a larger size. In this work, the 2nd-order inter-modulation (IM2) component of the two RF WPT tones is extracted to lock an on-chip oscillator, providing a low-jitter PVT-robust clock. In this way, the wireless systems can benefit from: 1) The clock recovery circuits operate at a low IM2 frequency, reducing the power consumption. 2) The WPT can be set to a high RF frequency to minimize the antenna. Fabricated in 65 nm CMOS process, the proposed crystal-less clock generator takes a small area of 0.023 mm2 in a wireless system chip. Measured results show -92 dBc/Hz@10 kHz phase noise and 6.8 μ W power.

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