This paper presents a 1.8-2.7 GHz low-power ring-oscillator-based fractional-N injection-locked digital PLL (IL-DPLL) in 40-nm CMOS for Internet-of-Things clock generation. A two-path injection technique is proposed to improve the in-band phase noise and the integrated jitter of the implemented PLL by 6 dB and 1.8×, respectively. Furthermore, a digital foreground calibration is introduced to effectively reduce reference spurs in a short calibration time of 2 μs. In the worst-case channel, the proposed DPLL using a 64 MHz reference input shows a 1.6 ps integrated jitter, -43.6 dBc reference spur, -45.8 dBc fractional spur and 1 kHz frequency resolution while consuming 1.33 mW power.