An implementation strategy for high-power, high resolution, fully digital transmitters (DTX) is proposed. It is based on a high-speed CMOS controller featuring a high-density flip-chip interconnect to an LDMOS power MMIC containing large arrays of custom low-VT LDMOS gate segments configured in RF-power switch banks. Using a two-level thermometer approach and a novel symmetric control scheme for the activation of the gate segments, a high-resolution 11-bit DTX switch bank is realized. It can provide peak RF powers >10 W at 45/40% peak drain/system efficiency at 3.525 GHz.@en

The RF performance of current-scaling digital transmitters (DTX) with polar, unsigned Cartesian, signed Cartesian, and multiphase architectures have been compared regarding power utilization of their output-stage switch banks and drain efficiency. The analysis includes various switch bank operation modes, such as switch bank sharing, segment activation interleaving, and their activation times (RF duty cycle of the segments). Current-scaling DTXs can be made compatible with high-power operations while offering high system efficiency and RF bandwidth. The average efficiency using Doherty power back-off efficiency enhancement is analyzed, and a comparison of the different proposed DTX implementations is presented.

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A high-power fully-digital Doherty transmitter (DDTX) is proposed. It features two segmented LDMOS output switch banks implemented in a custom V T -down-shifted LDMOS technology. A 40 nm CMOS controller digitally activates the individual LDMOS gate segments of the output stage at RF speed. An inverted Doherty power combiner is proposed that features non-short circuited 2 nd harmonic conditions for the main and peak switch banks to boost the RF bandwidth. To guarantee smooth output power and efficiency vs. frequency, a 2 nd harmonic trap is introduced in the power combiner, yielding an RF bandwidth of > 400 MHz. The realized demonstrator can achieve over 39 W peak output power. Its highest drain and system efficiencies, respectively 60 % and 57 %, were found at 34.2 W of output power, while in power back-off its peak drain and system efficiencies are 52 % and 48 % respectively. Over a 25 dB output range, the system efficiency is within 4 percent points of the drain efficiency.@en

This paper presents a low-loss load-insensitive Doherty power amplifier (DPA) technique. The proposed DPA is insensitive to ohmic load variation by adjusting its supply voltages and input drive of the main and peaking stages in a mirrored approach. Moreover, a low-loss tunable matching network (TMN) is employed to cancel out any reactive part of the load. To validate this technique, a printed circuit board (PCB) based demonstrator consisting of the Doherty PA, a six-port reflectometer, and a tunable shunt resonator have been fabricated. When subjected to a 50 Ω load, at the 1 dB compression point, the DPA delivers an output power of 32.3 dBm with a power gain and peak drain efficiency of 14.6 dB and 61 %, respectively. When the DPA is driven with a pre-distorted 64-QAM 4 MHz signal optimized for the 50 Ω loading condition, it delivers 24.4 dBm at 41 % average drain efficiency, with EVM/ACLR −40.9 dB / −46.9 dBc. Subsequently, when subjected to a 2:1 VSWR over a 0°−360° mismatch trajectory, using the unaltered 50 Ω DPD correction, it is capable of delivering an output power of 24.4 ± 0.1 dBm with a 34–39 % drain efficiency while maintaining an EVM/ACLR better than −32.3 dB / −39.3 dBc for all load conditions.@en

Fully digital transmitters (DTXs) have the potential of replacing analog-intensive transmitter (TX) line-ups in future massive multiple-input and multiple-output (mMIMO) systems since they hold the promise of higher system integration level and energy efficiency. DTX operation so far has been limited to low RF output powers. This article introduces a concept that enables high-power DTX operation. A DTX demonstrator targeting both high output power and high efficiency is realized as a proof of concept. It is based on a custom <formula> <tex>${V_{T}}$</tex> </formula> -shifted laterally-diffused MOS (LDMOS) technology, which is utilized to implement a segmented high-power output stage operated in class-BE. A low-voltage high-speed 40-nm CMOS controller drives the individual output stage segments at gigahertz rates. Measurements show the promising results for the proposed high-power DTX concept and provide valuable lessons for future DTX implementations.

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This article presents an efficient digital polar transmitter (DPTX) at mm-wave frequencies that exploit a novel N -way series Doherty combiner (SDC) to enhance its drain and system efficiency at deep power back-off (PBO). The proposed N -way SDC is scalable and can be implemented elegantly using N transformers and N-1 shunt capacitors. As a proof of concept, a four-way Doherty DPTX is realized with the proposed SDC in which four identical but independent digital phase modulators deliver a phase-modulated constant envelope signal to their corresponding digital power amplifiers to perform the required amplitude modulation. Fabricated in a 40nm CMOS process, the proposed DPTX occupies a core area of 1.1 mathrm {mm^{2}} and exhibits 18.7dBm saturated output power and <-40dBc LO feedthrough. It demonstrates a drain efficiency of 33%/36%/22% at 0/4.5/11.5dB PBO at a 29.5GHz carrier frequency. While transmitting a 300MHz 64-QAM OFDM signal with a peak-to-average power ratio of 10.7dB, the DPTX achieves 18%/8% average drain/system efficiency, -27.6dB error vector magnitude, and -27.5dBc adjacent channel leakage ratio. To the best of our knowledge, this work is the first reported mm-wave Doherty transmitter that includes the entire chain all the way from the binary data stream up to the modulated mm-wave output signal.

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An energy-efficient, intrinsically linear, digital class-C like operation-mode is investigated for use in high-power digital transmitters (DTXs), which target next generation mMIMO base stations that offer lower costs, higher integration, and improved system efficiency. The proposed operation utilizes class-B/C output matching in combination with duty-cycle reduction and current-mode operation of a segmented output stage. Its performance in terms of efficiency, output power, and linearity is benchmarked with analog class-B/C operation. The proposed digital class-C like operation has been experimentally verified using a fully-digital, dual TX line-up with VT-shifted segmented LDMOS output stages. All output stage segments are individually controlled by high-speed digital drivers implemented in 40 nm CMOS technology. The realized prototype provides 25.9 W (CW) output power with 75.7 % drain and 72.9 % system efficiencies, at 930 MHz and at 28 V drain supply.

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Recently, digital transmitters (DTXs) that feature arrays of controlled digital PA (DPA) cells have become increasingly popular since they directly benefit from nanoscale CMOS technology, yielding reduced die area and highly efficient operation [1] -[6]. For wideband applications, I/Q DTXs are considered superior over their polar counterparts due to their linear I/Q operation, which avoids bandwidth expansion. Nevertheless, I/Q DTXs can suffer from the interaction between their I and Q paths, especially at higher power levels, giving rise to an I/Q image and nonlinearity. To tackle this issue, an IQ interleaved upconverter has been introduced [1]. However, its 25%-LO requirement restricts the operational frequency to below 5GHz. The diamond-shaped mapping technique, presented in [2], uses 50% LOs and a different I and Q combining method but suffers from nonlinearity due to a clipping operation. Besides, the large peak-to-average power ratio (PAPR) in modern wireless standards requires the DTX to operate in deep power back-off (DPBO), degrading its average efficiency. To target applications requiring large modulation bandwidth, high spectral purity and average efficiency, we present a DTX with a signed IQ interleaved upconversion approach based on 50%-LO clock distribution, which enables close to perfect orthogonal I/Q summation. To enhance its average efficiency, a compact, 4-way Doherty DPA architecture is introduced.

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Fifth-generation (5G) mm-wave communication systems support high-order modulation schemes with large peak-to-average power ratios (PAPR). This demands transmitter (TX) operation in deep power back-off (PBO), thus degrading its average efficiency. Hence, several mm-wave Doherty PAs have been proposed [1], [3] to address this issue. However, the number of their peaking amplifiers (PAP) has been limited to two, mainly due to poor scalability, and high losses in the Doherty power combiner. Therefore, the efficiency enhancement was restricted to the 10dB PBO range. Furthermore, prior-art chiefly employed an analog class-AB amplifier for the main PA (PAM), degrading the system efficiency (SE) for two reasons. First, the conduction angle of an analog amplifier increases with a reduction of the drive signal amplitude, resulting in a Class-A-type efficiency roll-off that severely degrades the achievable PBO efficiency. Second, the output impedance of analog PAs is almost constant while the PAs' load significantly increases in PBO Doherty operation. This results in a load mismatch at PBO, degrading the PAs' gain and efficiency while giving rise to AM-AM and AM-PM distortion.

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A high-power digital transmitter (DTX) concept, targeting future low-cost, highly-integrated and energy-efficient mMIMO base stations, is presented. The proposed approach bridges the 'historical' gap between low-voltage high-speed digital and high-voltage high-power RF devices. The resulting combination allows for a complete replacement of the traditional TX line-up, which includes signal-generation, up-conversion, and analog pre-drivers and power amplifier (PA), as such, facilitating drastic energy savings. The DTX principles are demonstrated by a dual TX line-up implemented in a dedicated VT-shifted LDMOS technology. Each 11-bit DTX line-up features 15 thermometer and 7 binary-weighted LDMOS output-stage segments, which are individually controlled by digital logic and high-speed drivers implemented in 40 nm CMOS technology. The realized DTX prototype exploits a 2.1 GHz centered class-BE output matching network and provides, at 20 V drain supply, 18.5 W (CW) output power with 66.7 % drain and 60.4 % system efficiencies. The suitability of the concept to handle modulated signals is demonstrated for a two-tone signal (Δf = 80 kHz), yielding an 1M3 < -51.4dBc and a 10MHz 256-QAM signal, achieving an ACLR of -46.1 dBc and 1.2 % EVM.

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Stochastic resonance (SR) is a phenomenon in which noise can be employed to increase the performance of a system. It can e.g. be used to improve the performance of comparator-based circuits. This paper presents the analytical derivation of input-output relation, harmonic distortion, and noise behaviour of a 1-bit ADC using SR. Furthermore, the design of a new signal multiplier based on SR-ADCs is presented. The predicted behaviours are demonstrated by means of simulations. The work presented in this paper shows the potential for analog to digital conversion and integrated signal processing fully based on stochastic resonance.

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