An implementation strategy for high-power, high resolution, fully digital transmitters (DTX) is proposed. It is based on a high-speed CMOS controller featuring a high-density flip-chip interconnect to an LDMOS power MMIC containing large arrays of custom low-VT LDMOS gate segments configured in RF-power switch banks. Using a two-level thermometer approach and a novel symmetric control scheme for the activation of the gate segments, a high-resolution 11-bit DTX switch bank is realized. It can provide peak RF powers >10 W at 45/40% peak drain/system efficiency at 3.525 GHz.@en

This article introduces an N -way chain-weaver balanced power amplifier (PA) for millimeter-wave (mm-wave) phased-array transmitters (TXs). Taking advantage of the proposed combining network, an embedded impedance/power sensor is implemented, which can be utilized for output power regulation, built-in self-test, and load-based performance optimization. The proposed PA architecture offers linearity and gain robustness under the antenna's frequency/time-dependent voltage standing wave ratio (VSWR). In the event of impedance mismatch, the proposed PA provides N different loads equally distributed on the VSWR circle. Consequently, the performance of the PAs is the average of N PAs with N different loads, which makes this structure VSWR resilient. As a proof of concept, an eight-way chain-weaver balanced PA (BPA) is realized in 40-nm bulk CMOS technology, and it delivers 25.19-dBm PSAT with 16.19% PAE. The proposed PA supports a 2-GHz 64-QAM OFDM signal with 16-dBm average power, achieving - 25-dB error vector magnitude (EVM). The average EVM is better than - 30.3 dB without digital pre-distortion (DPD) for an '800-MHz 256-QAM OFDM' signal while generating an average output power of 12.17 dBm. The performance of the PA is also evaluated under 1.5:1-3:1 VSWR conditions. The measured small-signal gain variation under VSWR 3:1 is pm 0.7 dB. Moreover, assuming any frequency/time-dependent loading condition within the VSWR 3:1 circle, the proposed chain-weaver BPA achieves < 2.8 {circ} amplitude-to-phase (AM-PM) over 3-GHz bandwidth. Besides, the embedded impedance/power sensor accuracy outperforms the state of the art. The proposed impedance sensor can measure VSWR 3:1 by the maximum angle and magnitude errors of 12.3 {circ} and 0.106, respectively.

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A wideband harmonic rejection voltage-domain mixer using resistive scaling is presented with excellent linearity and high IF bandwidth. Thin-oxide devices with constant gate-to-source voltages (VGS) are utilized to maximize the switching linearity. A novel switching core topology providing low-impedance IF outputs is proposed to support wideband in-phase (I) and quadrature (Q) mixer outputs when loaded by ADCs. Eight LO clock phases, each with a 25 % duty cycle, are on-chip generated for quadrature down-conversion and harmonic rejection (HR). By cleverly activating and organizing the mixer branches, the RF mixer input impedance can be kept perfectly constant throughout all eight clock phases, enhancing the mixer’s linearity. The TSMC 40 nm-CMOS realized mixer reaches 20.9 dBm OIP3 at an IF of 50 MHz with a conversion loss of 22.5 dB. It offers an 800 MHz 3-dB IF bandwidth at a differential capacitive loading of 0.15 pF, with a total power consumption of 40.7 mW drawn from a 1.1 V supply. The mixer targets linear wideband base station observation receiver applications.@en

The RF performance of current-scaling digital transmitters (DTX) with polar, unsigned Cartesian, signed Cartesian, and multiphase architectures have been compared regarding power utilization of their output-stage switch banks and drain efficiency. The analysis includes various switch bank operation modes, such as switch bank sharing, segment activation interleaving, and their activation times (RF duty cycle of the segments). Current-scaling DTXs can be made compatible with high-power operations while offering high system efficiency and RF bandwidth. The average efficiency using Doherty power back-off efficiency enhancement is analyzed, and a comparison of the different proposed DTX implementations is presented.

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With the rise in communication capacity, deep neural networks (DNN) for digital pre-distortion (DPD) to correct non-linearity in wideband power amplifiers (PAs) have become prominent. Yet, there is a void in open-source and measurement-setup-independent platforms for fast DPD exploration and objective DPD model comparison. This paper presents an open-source framework, OpenDPD, crafted in PyTorch, with an associated dataset for PA modeling and DPD learning. We introduce a Dense Gated Recurrent Unit (DGRU)-DPD, trained via a novel end-to-end learning architecture, outperforming previous DPD models on a digital PA (DPA) in the new digital transmitter (DTX) architecture with unconventional transfer characteristics compared to analog PAs. Measurements show our DGRU-DPD achieves an ACPR of -44.69/-44.47dBc and an EVM of -35.22dB for 200MHz OFDM signals. OpenDPD code, datasets and documentation are publicly available at https://github.com/lab-emi/OpenDPD

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Digital predistortion (DPD) enhances signal quality in wideband radio frequency (RF) power amplifiers (PAs). As signal bandwidths expand in modern radio systems, DPD's energy consumption increasingly impacts overall system efficiency. Deep neural networks (DNNs) offer promising advancements in DPD, yet their high complexity hinders their practical deployment. This article introduces open-source mixed-precision (MP) neural networks that employ quantized low-precision fixed-point parameters for energy-efficient DPD. This approach reduces computational complexity and memory footprint, thereby lowering power consumption without compromising linearization efficacy. Applied to a 160-MHz-BW 1024-QAM OFDM signal from a digital RF PA, MP-DPD gives no performance loss against 32-bit floating-point precision DPDs, while achieving -43.75 (L)/-45.27 (R) dBc in the adjacent channel power ratio (ACPR) and -38.72 dB in error vector magnitude (EVM). A 16-bit fixed-point-precision MP-DPD enables a 2.8× reduction in estimated inference power. The DPD code in PyTorch is publicly available on GitHub.

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This article introduces a single-supply balun-first three-way parallel Doherty power amplifier (PA) tailored for millimeter-wave (mm-wave) fifth-generation (5G) applications. It incorporates a bandwidth enhancement technique that widens the operational frequency range, enhances broadband power back-off (PBO) efficiency, and reduces impedance mismatch between differential PAs. Realized in 40-nm CMOS bulk technology with a core area of 0.77 mm2 , the prototype delivers a saturated power/peak gain surpassing 20 dBm/16 dB, and it demonstrates a drain efficiency (DE) exceeding 15%/22%/33% at 9.5 dB/6 dB/0 dB PBO across a 24–30 GHz band. The proposed mm-wave PA achieves EVM/ACLR values of − 24.3 dB/ − 30.1 dBc for a 1-GHz 64-QAM OFDM signal, operating at an average output power (Pout) of 9.4 dBm with an average DE of 15%. For a 50-MHz 1024-QAM OFDM signal, it achieves an average Pout/DE of 8.6 dBm/12% with EVM/ACLR of − 30 dB/ − 36.3 dBc.@en

This article presents an inverted Doherty power amplifier (IDPA) made load insensitive up to 2:1 voltage standing wave ratio (VSWR) across its fractional bandwidth with a very compact wideband impedance sensor embedded in its output power-combining network (OPCN). To correct for load variation, a low-loss tunable resonator (TR) is used to ensure ohmic loads to the main and peaking stages at the center frequency of operation. At off-center frequencies, TR is used to present an ohmic load for the main stage, while a digitally adjustable phase shifter is used to (re)align the main and peaking stage's current summation in the OPCN. For ohmic load deviations, the main and peaking stage supply voltages and input drives are adjusted to maintain the ideal Doherty's output power and efficiency profile related to nominal 50Ω loading across the bandwidth. To implement the control of the formerly mentioned technique, a wideband impedance sensor is proposed, which uses the orthogonality of incident and reflected waves and requires only four peak detectors. As proof of principle, a prototype 850-950-MHz IDPA featuring the proposed correction technique, the impedance sensor, and the control loop has been implemented as a printed circuit board (PCB) demonstrator. Measurement results show that the IDPA can maintain constant output power with a tolerance of only ± 0.2 dB while improving the drain efficiency and linearity across the entire fractional bandwidth (11% ) for a VSWR range of 2:1.

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Recently, the so-called sub-6GHz band of the 5G new radio (NR) has been extended to 7.125GHz to address the relentless customer demand for higher data-rate communication. This demands a new design approach for the local area base-station (LA-BS) receivers (RXs) to cover a wide operating frequency range of 0.41 to 7.125GHz. Moreover, for NR bands above 3GHz, the maximum RF bandwidth (BW) is as high as 400MHz, in which a -35dBm modulated in-band (IB) blocker can be present. These impose stringent BW and IB linearity requirements for the baseband amplifiers in the LA-BS receivers. In addition to IB interferences, a -15dBm continuous-wave (CW) out-of-band (OOB) close-in blocker can also be present at 60MHz offset frequency from the passband edges, thus demanding a highly selective RX. Finally, the blocker 1dB compression point (B1textdB) becomes a key parameter for local area co-location applications in which the power of the far-out OOB blocker can be as large as -4dBm.

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This paper presents a 40nm CMOS mm-wave 3-way Doherty power amplifier (PA) suitable for 5G mm-wave transmitters. It features a bandwidth-enhanced technique using a compact single-supply balun-first 3-way Doherty combiner. The realized front-end with a core area of 0.77 mm2delivers a peak power/gain of more than 20 dBm/16 dB and a drain efficiency (DE) of better than 15 %/22 %/33 % at 9.5 dB/6 dB/0 dB power back-off across a 24-to-30 GHz band. At 26 GHz, it achieves an EVM/ACLR of -23.5 dB/-29.5 dBc for an 800MHz 64-OFDM signal with 9.8 dBm average output power and a 15 % average DE.

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By introducing three different techniques, this article, for the first time, presents a wideband highly linear receiver (RX) capable of handling blocking scenarios in fifth-generation (5G) microcell base station applications. First, a parallel preselect filter is introduced to satisfy the base station co-location blocking requirements. Next, a combination of third-order RF and baseband (BB) filters is adopted to attenuate close-in blockers by a -120 dB/dec roll-off. Finally, a translational feedback network is proposed to reduce the in-band gain ripple to below 0.5 dB and provide better than -19 dB input matching. Fabricated in the 40-nm CMOS technology, the proposed RX occupies a core area of 0.8 mm2 and consumes 108-176 mW from a 1.3 V supply over the RX's 0.5-3-GHz operating frequency. It achieves a 3-dB bandwidth of 150 MHz and a noise figure (NF) of 2.6-3.9 dB over the RX frequency range. Activating the parallel preselect filter degrades the NF by as little as 1.2 dB in the worst case. The RX shows a ≥q 97.5% throughput when receiving a 100-MS/s quadrature phase shift keying (QPSK) signal with 7.5-dB SNR and achieves a -9.7 dB error vector magnitude (EVM) while facing a -15 dBm continuous-wave (CW) blocker only 20 MHz away from the desired 100-MS/s QPSK signal with 12.3-dB SNR, thus satisfying the 3rd generation partnership project (3GPP) requirements with sufficient margin.

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This article presents a wideband, energy-efficient digital transmitter (DTX) suitable for multi-mode/multi-band wireless communication applications. It features various operation modes comprising Cartesian (Modes-1/-2) and multi-phase (Modes-3/-4) configurations utilizing LO clocks with different duty cycle in the interleaving/non-interleaving configurations. The multi-phase operation compromises polar and Cartesian features by mapping the I/Q signals into two non-orthogonal basis vectors with a 45° relative phase difference and a 3-bit phase selector scheme. The different operation modes are extensively analyzed and compared. Fabricated in a 40-nm CMOS process with an off-chip matching network, the proposed DTX occupies a core area of 0.72 mm2 and delivers 23.18-dBm RF peak power at 2.1 GHz from a 0.95-V supply voltage with drain/system efficiencies of 66.26%/52.59%, respectively. Utilizing a simple memory-less digital pre-distortion (DPD) for a 160-MHz four-channel 64-quadrature amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM) signal, the DTX delivers an average P Out of 13.5/11.4/7.7/9.4 dBm, achieving an adjacent channel (power) ratio (ACL(P)R) of better than -42/-40/-40/-38 dBc and an average error vector magnitude (EVM) of -36/-34/-34/-32 dB, operating in Modes-1/-2/-3/-4, respectively. While transmitting a 200-MHz single-channel 256 (1024)-QAM OFDM signal at 2.4 GHz in Modes-1/-4, the average delivered output power is 14.11/9.29 (12.23/7.32) dBm with average drain and system efficiencies of 33.17%/26.3% (23.82%/22.83%) and 24.81%/22.85% (19.34%/18.81%), while the ACLR and EVM are better than -42/-41 (-43/-43) dBc and -34.6/-33.1 (-33.5/-33.9) dB, respectively.

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This paper presents an advanced yet simple digital pre-distortion (DPD) technique for digital I/Q transmitters (DTXs). Exploiting the I/Q orthogonality, an effective 2×1-D DPD procedure is proposed to bypass the exhaustive 2-D search of the entire constellation diagram. Utilizing this technique, a four-way Doherty DTX is linearized. Measurement results demonstrate that for a non-contiguous six-carrier OFDM-QAM signal with aggregated bandwidth of 150MHz, the ACPR is better than -47.3dBc, and EVM is better than -41/-40dB for channel-1/-6, respectively.

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This article presents a wideband blocker tolerant receiver (RX) for fifth-generation (5G) user equipment applications. Two programmable zeros around the channel bandwidth are introduced to sufficiently suppress the close-in blockers of 5G applications. Since the effect of zeros gradually diminishes at larger out-of-band offset frequencies, an auxiliary current-sinking path is also introduced to reduce the RX input impedance at far-out offset frequencies. Moreover, a simple second-order transimpedance amplifier (TIA) is adopted to enhance the proposed RX selectivity. The utilized TIA synthesizes two complex conjugate poles to achieve a flat gain response and -40 dB/dec roll-off. A 40-nm CMOS RX prototype occupies 1.15mm2 and consumes 84-140mW from a 1.3-V supply voltage over the 0.5-3-GHz operating frequency range. The RX achieves a 160-MHz RF bandwidth, 2.6-4.2-dB noise figure, a -0.3-dBm blocker 1-dB compression point (B1dB), and an out-of-band third-order intercept point (IIP3) of 22.5 dBm. As a test case, using the 3GPP standard, a -15-dBm continuous wave (CW) close-in out-of-band blocker located at 85-MHz offset from the passband edges is applied to the RX. Thanks to the receiver's high selectivity, the RX achieves 100% throughput while detecting 100-MS/s quadrature phase shift keying (QPSK) signal with 16 dB higher power than the reference sensitivity.

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A current-mode direct-digital RF modulator (DDRM)-based transmitter (TX) architecture is proposed in this article for energy-efficient wireless applications. To demonstrate its key principles, a 2×13 bit demonstrator is implemented in a 40-nm CMOS technology. This DDRM can operate standalone or as a driver for a common-gate (CG)/common-base (CB) power amplifier (PA). The proposed DDRM is based on current-steering radio frequency digital-to-analog converters (RFDACs) that feature an extra current division path to allow the generation of the optimum current-mode class-B drive profile for the final CG/CB PA, facilitating energy-efficient TX operation without compromising linearity. For this purpose, the DDRM uses signed-IQ mapping combined with a class-B harmonic rejection (HR) technique. In addition, an advanced dynamic biasing technique is introduced to further enhance the TX line-up efficiency in deep power back-off (PBO) region. The DDRM driver standalone can provide 19.6-dBm RF peak output power. It supports a '160-MHz 256-QAM' signal at 2.4 GHz with an adjacent channel leakage ratio (ACLR) of -40.3 dBc and an error vector magnitude (EVM) of -33 dB, without using any digital pre-distortion (DPD). When connected to a CB SiGe PA, the overall TX line-up achieves an output power of 27 dBm and an overall TX system efficiency of 20%. This DPD-free TX line-up achieves an ACLR of -37.7 dBc and an EVM of -30 dB, respectively, when operating with an '80-MHz 64-QAM' signal at 2.2 GHz.

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This paper proposes a power amplifier (PA) correction technique to recover from load mismatch. It utilizes a main PA, two auxiliary PAs, and a coupler. By adjusting the input drive levels of the PAs it can recover the output power and to a great extent the efficiency of the main PA even when exposed to 2:1 VSWR mismatch conditions. When connected to 50O loading, only the main PA is active, for impedances below or above 50 O, besides the main amplifier, one of the auxiliary PAs is also activated. The power generated by the auxiliary PA adds in phase to the output power of the main PA, as such allowing the output power to be constant at the expense of a minor efficiency penalty.

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To support wideband complex modulated signals and comply with the stringent requirements of modern communication standards in an energy-efficient manner, recently, digital transmitters (DTXs) have been explored to fully benefit from the high-speed switching and integration capabilities of nanoscale CMOS technologies [1]–[5]. These DTXs are primarily exploiting a polar or Cartesian architecture. In a polar DTX [1], [2], two eigenvectors of amplitude (p) and phase $(\phi)$ are generated from the in-phase (I) and quadrature (Q) baseband signals using non-linear coordinate rotation transformations (i.e., CORDIC). Provided that $\rho$ is constant, the achievable drain efficiency (DE) is constant (Fig. 1 top). However, polar $\text{DTXs}$ cannot manage large modulation bandwidth due to their non-linear $\mathrm{I}/\mathrm{Q}$ to $\rho/\phi$ conversion. Moreover, their phase and amplitude paths must recombine at the output stage without any delay mismatch to maintain linear operation. In contrast, Cartesian DTX variants can handle signals with large modulation bandwidth [3]. Nevertheless, their DE is lower than their polar counterparts owing to the linear combination of orthogonal I/Q vectors, yielding a 3-dB worst-case output power loss at the orthogonal (I/Q) axes. Alternatively, a multi-phase operation can be utilized that compromises polar and Cartesian features by mapping the I/Q signals into two non-orthogonal basis vectors with 45° relative phase difference and magnitudes of $\mathrm{I}_{\text{MP}}=\mathrm{I}-\mathrm{Q}$, QMP $=\sqrt{2}\mathrm{Q}$ [4]. This architecture inherits the advantages of the cartesian DTX, such as wideband operation, symmetrical, and synchronized $\mathrm{I} /\mathrm{Q}$ paths along with a DE behavior that imitates the polar case. This paper presents a multi-mode DTX that uses both Cartesian and multi-phase operation modes to target applications requiring large modulation bandwidth, decent spectral purity and average efficiency.@en

A high-power fully-digital Doherty transmitter (DDTX) is proposed. It features two segmented LDMOS output switch banks implemented in a custom V T -down-shifted LDMOS technology. A 40 nm CMOS controller digitally activates the individual LDMOS gate segments of the output stage at RF speed. An inverted Doherty power combiner is proposed that features non-short circuited 2 nd harmonic conditions for the main and peak switch banks to boost the RF bandwidth. To guarantee smooth output power and efficiency vs. frequency, a 2 nd harmonic trap is introduced in the power combiner, yielding an RF bandwidth of > 400 MHz. The realized demonstrator can achieve over 39 W peak output power. Its highest drain and system efficiencies, respectively 60 % and 57 %, were found at 34.2 W of output power, while in power back-off its peak drain and system efficiencies are 52 % and 48 % respectively. Over a 25 dB output range, the system efficiency is within 4 percent points of the drain efficiency.@en

This article presents an efficient digital polar transmitter (DPTX) at mm-wave frequencies that exploit a novel N -way series Doherty combiner (SDC) to enhance its drain and system efficiency at deep power back-off (PBO). The proposed N -way SDC is scalable and can be implemented elegantly using N transformers and N-1 shunt capacitors. As a proof of concept, a four-way Doherty DPTX is realized with the proposed SDC in which four identical but independent digital phase modulators deliver a phase-modulated constant envelope signal to their corresponding digital power amplifiers to perform the required amplitude modulation. Fabricated in a 40nm CMOS process, the proposed DPTX occupies a core area of 1.1 mathrm {mm^{2}} and exhibits 18.7dBm saturated output power and <-40dBc LO feedthrough. It demonstrates a drain efficiency of 33%/36%/22% at 0/4.5/11.5dB PBO at a 29.5GHz carrier frequency. While transmitting a 300MHz 64-QAM OFDM signal with a peak-to-average power ratio of 10.7dB, the DPTX achieves 18%/8% average drain/system efficiency, -27.6dB error vector magnitude, and -27.5dBc adjacent channel leakage ratio. To the best of our knowledge, this work is the first reported mm-wave Doherty transmitter that includes the entire chain all the way from the binary data stream up to the modulated mm-wave output signal.

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This letter presents a novel load-modulation-based 3rd-order intermodulation distortion (IMD3) cancellation technique for class-B CMOS power amplifiers (PAs). In a class-B PA, the IMD3 generated by the 3rd-order transconductance ( $g_{m3}$ ) and the gain compression have opposite signs, and thus, they can cancel each other at specific bias and loading conditions. The proposed Doherty topology allows adjusting the gain compression by modulating the effective loading, facilitating IMD3 cancellation over the entire load modulation region. The proposed approach is verified using a 28 GHz 40 nm CMOS series-Doherty PA (DPA) topology. The experimental result demonstrates 10/17 dB IMD3 improvement compared to class-B/DPA operation. Without using any digital pre-distortion, the measured EVM of the proposed technique for a 50 MHz 64-QAM OFDM signal with 8.9 dBm average output power is -38.7 dB (1.2%), which is 5.7/11 dB better than a standard class-B/DPA operation.

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