This report demonstrates an innovative method to achieve large scale 20 μm pitch Cu-Cu direct bonding, utilizing lithographic stencil printing to transfer small-sized nano-copper (CuNPs) paste and employs a thermocompression method for CuNPs sintering to establish interconnections between copper-pillars and CuNPs bumps. Shear tests were conducted to characterize the bonding strength. High-throughput 20 μm pitch copper-to-copper direct bonding enables lower annealing temperatures for bulk-Cu to bulk-Cu bonding. Lithographic stencil printing is used to transfer the CuNPs paste, followed by sintering of the nanoparticles to establish interconnections. Shear tests and cross-section SEM were conducted to characterize the bonding strength and quality.

@en

This study presents a dual approach combining molecular dynamics simulations and experimental analysis to explore the sintering behavior of copper (Cu) nanoparticles. Our simulation model comprises 240 nanoparticles, through which we systematically examine the coalescence kinetics during the sintering process. The simulations provide a detailed view of the particle interactions, structural evolution, and the mechanisms driving nanoparticle fusion at the atomic level. Complementing the simulations, we conducted 3D reconstructions using Focused Ion Beam Scanning Electron Microscopy (FIB-SEM) to characterize the microstructure of the sintered nanoparticles. This hybrid approach not only deepens our understanding of the fundamental processes governing the sintering of Cu nanoparticles but also bridges the gap between theoretical predictions and experimental observations, offering insights into the optimization of sintering processes in practical applications.

@en

The trend to 3D and heterogeneous integration enable driving multi-functional blocks in one package. Flip-chip integration is currently playing an important role and is based on solder joints. To overcome the limitations of solder joints, all-copper interconnects have been investigated to meet electrical, thermal, and reliability demands in 3D integration. The underfill process is widely applied in flip-chip encapsulation technology. We propose a novel wafer-scale all-Cu interconnect method combining epoxy-based photo-patternable polymer as self-aligned underfill layer with the patterned copper nanoparticles interconnects. The resulting test wafers were able to pattern 20 µm pitch copper nanoparticle-paste interconnects on both substrates with and without photoimageable polymer. The Cu paste was applied to form the interconnects and was sintered after bonding process. Free-standing nanocopper is sintered to obtain mechanical properties with a Young's modulus of 112 GPa. All-Cu interconnects with diameter of 50 µm and 100 µm were measured to achieve the specific contact resistance, ranging from 1.4 × 10-5O· cm2 to 1.0 × 10-5O· cm2 at different sintering temperature when epoxy-based underfill existing. And its resistivity was 4.54× 10-4 O· cm, compared to 5.86× 10-4O· cn for the all-Cu interconnects without underfill.

@en

Copper nanoparticles (CuNPs) sintering for flip-chip interconnects is a promising solution for 3D and heterogeneous integration to overcome the limitation of solder materials. To this end, we perform the photolithographic stencil printing method to pattern CuNPs, and the form of flip-chip interconnects is completed after CuNPs sintering process. This paper aims to study the effect of sintering processing parameters (time, pressure, temperature) on the mechanical properties of CuNPs bumps when applying the novel method to approach the Cu interconnects. We fabricated seven groups of specimens of sintered CuNPs bumps, built with a diameter of 100 μm and sintered. The nanoindentation tests assessed the mechanical property to get Young's modulus and hardness. Results clarify that Young's modulus is strongly affected by pressure. An suggested combination of parameters (the 25 MPa and 260 °C for 15 min) give the highest modulus of 126 GPa and the hardness of 1.76 GPa. Moreover, the observations by scanning electron microscopy (SEM) reveal the microstructure and porosity evolution versus different processing parameters.

@en

Advances in semiconductor device manufacturing technologies are enabled by the development and application of novel materials. Especially one class of materials, nanoporous films, became building blocks for a broad range of applications, such as gas sensors and interconnects. Therefore, a versatile fabrication technology is needed to integrate these films and meet the trend towards device miniaturization and high integration density. In this study, we developed a novel method to pattern nanoporous thin films with high flexibility in material selection. Herein, Au and ZnO nanoparticles were synthesized by spark ablation and printed on a Ti/TiO2 adhesion layer, which was exposed by a lithographic stencil mask. Subsequently, the photoresist was stripped by a cost-efficient lift-off process. Nanoporous patterned features were thus obtained and the finest feature has a gap width of 0.6 μ fm and a line width of 2 μ fm. Using SEM and profilometers to investigate the structure of the films, it was demonstrated that the lift-off process had a minor impact on the microstructure and thickness. The samples presented a rough surface and high porosity, indicating a large surface-to-volume ratio. This is supported by the measured conductivity of Au nanoporous film, which is 12% of the value for bulk Au. As lithographic stencil printing is compatible with conventional lithographic pattering, this method enables further application on mass production of various nanoporous film-based devices in the future.

@en

The continuous trend to integrate more multi-functions in a package often involves, Heterogeneous Integration of multi-functional blocks in some kind of 3D stacking. The conventional flip chip for die-on-substrate technology applies solder for integration. However, solder joint integration has the disadvantages of restricting height, reflow issues and re-melting at high operating temperatures. Nanometallic particle sintering offers a potential solution for these solder related issues. Nanometallic particle sintering occurs at low temperature and does not reflow and melt at higher temperatures. Hence, it can be applied for quite precise alignment and integration technologies, such as photonic components on silicon for harsh environment applications. In order to test this concept, we use sapphire and Si wafers with different mechanical properties, which can lead to the coefficient of thermal expansion mismatch. The sapphire chip can operate at a higher temperature applied for ultraviolet photonics application. This report describes a novel approach using copper nanoparticles paste patterned through photolithographic stencil printing. The photoresist acts as the stencil mask, and a photoresist lift-off process is applied to strip the photoresist stencil. This process has the advantages of lithographic form factor and precision and provides a chip to chip interconnect with a standard height of 20 µm.@en