The photovoltaic (PV) market is currently dominated by crystalline silicon (c-Si) technology, which accounts for 95% of the production. However, the record single-junction c-Si solar cell has achieved a record efficiency of 26.81% approaching the theoretical efficiency limit of 2
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The photovoltaic (PV) market is currently dominated by crystalline silicon (c-Si) technology, which accounts for 95% of the production. However, the record single-junction c-Si solar cell has achieved a record efficiency of 26.81% approaching the theoretical efficiency limit of 29.43%. In an effort to overcome this barrier, multi-junction devices are being investigated, and perovskite/Si tandem technology is attracting a lot of interest. This is because it is compatible with well-established c-Si technology and is comparatively less expensive. Recently, two-terminal (2T) monolithic tandem devices with a c-Si bottom cell and a perovskite top cell have achieved an impressive 33.7% efficiency. By utilizing a solution-based process it allows for fabricating high-quality perovskite layers. However, problems develop when the bottom cell’s light trapping features exceed the thickness of the perovskite layer. To ensure uniform coverage of high-quality perovskite layer, the light trapping features must be lowered to sub-micrometre (< 1 μm) height.
This thesis investigates three methods for creating sub-micron features on the c-Si bottom cell. The first two approaches include wet-chemical processing from the top-down and bottom-up techniques. Using a poly-Si etch solution, the top-down approach aims to lower the height of large surface features from 3-5 μm to less than 1 μm. This method resulted in substantial reflection losses and poor passivation due to surface-induced roughness, even though the peak height was lowered to 0.9 μm. In order to tackle this issue, an additive was added to the mixture, producing a morphology with a 1.1 μm lower peak height, compared to an initial peak height of 3 μm. Further, the passivation has seen a two-fold increase in minority carrier lifetime. This increase is attributed to the reduced surface roughness that was inspected through SEM images. However, the surface still contained nano-scale features whose origination could be related to the cleaning procedure followed or the (i)a-Si:H layer growth. The second method is a bottom-up approach and uses KOH, K2SiO3, and a surface additive to create sub-micron features on a flat Siwafer. Once the chemical concentrationswere optimized, the peak height was effectively lowered to less than 0.8 μm at an F-ratio of F = 2.0. But, this experiment is conducted at a temperature of 80◦ C. Many non-uniformities in pyramid distribution were observed as well as nano-scale roughness for F-ratio of F=0. This seemed to be resolved with better pyramid homogeneity and reduced nano-scale roughness by lowering the temperature to 70◦ C. While, maintaining a peak height below 0.8 μm at F=2.0. Moreover, this approach also exhibited lower reflection losses which is close to reflection observed from large pyramidal features (˜3μm).
The last method includes the use of lithography to produce 2D periodic inverted nano pyramids. This process flow showed that patterns with critical dimensions close to 100 nm may be transferred using high-throughput nano-imprinting lithography. By using a much rigid soft mold that did not showcase any pattern distortion. However, the limitations in mask opening created issues with the nano-pyramid formation. This further requires the optimization of suitable hard mask layers. To sum up, these methods demonstrate the possibility of producing effective sub-micron features, which is promising for perovskite/Si tandem technological advancements.