LS

L Sousa

13 records found

An improved RNS reverse converter for the {2 2n+1-1, 2n, 2n-1} moduli set

Residue-to-binary converters for the moduli set {2 2n+1, 2 2n, 2n-1}

On-the-fly attestation of reconfigurable hardware

Cost-efficient SHA hardware accelerators

Merged computation for whirlpool hashing

Low power microarchitecture with instruction reuse

BRAM-LUT tradeoff on a polymorphic DES design

Dynamic FPGA reconfigurations with run-time region delimitation

Reconfigurable cryptographic processor

Rescheduling for optimized SHA-1 calculation

Improving SHA-2 hardware implementations

Reconfigurable memory based AES co-processor

Polymorphic AES encryption implementation