The nanoindentation test was conducted in this paper to investigate the indentation hardness, plasticity and initial creep properties of pressure sintered nanosilver joint at various test temperatures. The effects of strain rate on the indentation hardness were first investigated. Then yield stress of nanosilver sintered joint was studied in various pressures sintered joints and the corresponding plastic stress-strain constitutive equations were gained. The maximum indentation depth of nanosilver sintered joint was obviously affected by the test temperature and sintering pressure. The indentation hardness of nanosilver sintered joint decreased with increasing test temperature from 140 to 200°C, which can be attributed to the increased amount of thermal vacancies at high temperatures. However, the indentation modulus exhibited decrease trend as the temperature increased. It is suggested that the distance between adjacent atoms was enlarged at elevated temperatures and furtherly resulted in the decrease of indentation modulus. In addition, the increased sintering pressure from 5 to 30 MPa improved the indentation hardness and modulus of sintered joint. The initial creep was observed in nanosilver sintered joint at temperatures ranged from 140 to 200°C. The increase of sintering pressure improved the resistance to creep of nanosilver sintered joint.

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Eutectic Sn58Bi (SnBi) solder paste mixed with 0 wt.%, 3 wt.%, 5 wt.%, 8 wt.% and 15 wt.% of Sn-3.0Ag-0.5Cu (SAC) paste was prepared by mechanical mixing. The effects of SAC paste additions on the microstructure evolution of SnBi-SAC/Cu composite solder joints during isothermal aging were investigated. The results indicated that the number of large Bi-rich phases decreased and the relative areas of β-Sn increased with increasing SAC content. Moreover, 1-μm Bi-rich particles were found near the Bi-rich phases. During the isothermal aging process, the diameter of the 1-μm Bi-rich particles in the solder bulk increased by about 50% with aging time by Ostwald ripening. The thickness of the interfacial intermetallic compound in all the solder joints increased slightly during the aging process. The formation of Cu₆Sn₅ was suppressed by the Bi-rich phases above the Cu₆Sn₅ layer with the aging time increasing. In addition, the solder bulk showed many cracks along the β-Sn grain boundaries after isothermal aging when the content of SAC paste was 5 wt.%. With 8 wt.% or 15 wt.% SAC, fractures were more obvious near the interface than away from the interface.

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Modern power electronics has the increased demands in current density and high-temperature reliability. However, these performance factors are limited due to the die attach materials used to affix power dies microchips to electric circuitry. Although several die attach materials and methods exist, nanosilver sintering technology has received much attention in attaching power dies due to its superior high-temperature reliability. This paper investigated the sintering properties of nanosilver film in double-side sintered power packages. X-ray diffraction results revealed that the size of nanosilver particles increased after pressure-free sintering. Compared with the pressure-free sintered nanosilver particles, the 5-MPa sintered particles showed a higher density. When increasing sintering pressure from 5 to 30 MPa, the shear strength of the sintered package increased from 8.71 to 86.26 MPa. When sintering at pressures below 20 MPa, the fracture areas are mainly located between the sintered Ag layer and the surface metallization layer on the fast recovery diode (FRD) die. The fracture occurs through the FRD die and the metallization layer on the bottom molybdenum substrate when sintering at 30 MPa.

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Purpose: Crack and stress distribution on dies are key issues for the pressure-assisted sintering bonding of power modules. The purpose of this research is to build a relationship among stress distributions, sintering sequences and sintering pressures during the sintering processes. Design/methodology/approach: Three sintering sequences, S(a), S(b) and S(c), have been designed for the double-side assembly of power module in this paper. Experiments and finite element method (FEM) analysis are conducted to investigate the crack and stress distribution. Findings: The sintering sequence had significant effects on the crack generation in the chips during the sintering process under 30-MPa pressure. The simulation results revealed that the module sintered by S(a) showed lower chip stress than those by the other two sintering sequences under 30 MPa. In contrast, the chip stress is the highest when the sintering sequence follows S(b). The simulation results explained the crack generation and prolongation in the experiments. S(a) was recommended as the best sintering sequence because of the lowest chip stress and highest yield rate. Originality/value: This study investigated the stress distributions of the double-side sintered power modules under different sintering pressures. Based on the results of experiments and FEM analysis, the best sintering sequence design is provided under various sintering pressures.

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This study investigated the interfacial reaction, the microstructure, and the hardness of the SAC305-xNi solder on both Cu and graphene-coated Cu (G–Cu) substrates. The experimental results indicate that the increase of Ni content in the solder leads to the roughness of the (Cu, Ni)6Sn5 IMC layer on Cu. In contrast, the growth of the (Cu, Ni)6Sn5 interfacial IMC, which results from increasing Ni addition, is significantly suppressed on G–Cu substrates. As the concentration of Ni ranges from 0 to 0.2 wt%, the microstructure of the solder bulks on Cu substrates shows slight changes. The hardness of the solder bulks in SAC305-Ni/Cu is similar to that in the SAC305/Cu solder joint. The amount of β-Sn rises and the eutectic area shrinks due to increasing Ni addition in the solder bulks on G–Cu substrates. Therefore, the solder bulks in the SAC305-Ni/G–Cu show lower hardness than that in the SAC305/G–Cu solder joint.@en

In this study, SAC305 and SAC305-0.3Ni solder balls were soldered onto Cu, high temperature treated Cu (H-Cu) and graphene coated Cu (G-Cu) substrates, respectively. The microstructure, the interfacial reaction, and the hardness of the solder joints were investigated. The interfacial intermetallic compound (IMC) is Cu₆Sn₅ in the solder joints of SAC305/Cu, SAC305/H-Cu, and SAC305/G-Cu. With the addition of 0.3 wt% Ni in the SAC305 solder, the interfacial IMC on Cu, H-Cu, and G-Cu transforms from Cu₆Sn₅ into (Cu, Ni)₆Sn₅. The thickness of Cu₆Sn₅ and (Cu, Ni)₆Sn₅ is the lowest on G-Cu substrate. Meanwhile, smooth (Cu, Ni)₆Sn₅ interfacial IMC layers are obtained in SAC305-0.3Ni/H-Cu and SAC305-0.3Ni/G-Cu solder joints. Both the SAC305 and the SAC305-0.3Ni solder bulks have the highest β-Sn content and the lowest concentration of eutectic phases on G-Cu substrate. Consequently, the hardness of the solder bulks on G-Cu is lower than that on the other two kinds of substrates.

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Purpose
- The purpose of this paper is to discuss the possibility of using soldering process for the bonding of chip-on-flexible (COF) light-emitting diode (LED) packages to heat sinks. The common bonding materials are thermal conductive adhesives. For thermal performance and reliability concerns, Tin-Bismuth (SnBi) lead-free solder paste was used for the connection of the COF packages and the Cu heat sinks by a soldering process in this study. Meanwhile, the geometrical effect of the SnBi solder layer on the thermal performance was also investigated.
Design/methodology/approach
- The effects of the bonding materials and the area of the solder layers on the thermal performance of the LED modules were investigated by finite element simulation and experimental tests.
Findings
– The SnBi soldered modules show much lower thermal resistance at the bonding layers than the adhesive-bonded LED module. Vertical heat transfer from the LED chips to the heat sinks is the primary heat dissipation mode for the SnBi soldered modules. Thus, the LED module with local solder layer shows similar LED thermal performance with the full-area soldered module. Meanwhile, the local soldering process decreases the possibility to form randomly distributed defects such as the large area voids and residue flux in the solder layers.
Research limitations/implications
– The research is still in progress. Further studies mainly focus on the reliability of the samples with different bonding materials.
Practical implications
– COF package is a new structure for LED packages. This study provides a comparison between SnBi solder and adhesive material on the thermal performance of the LED. Meanwhile, the authors optimized the geometrical design for the solder layer. The study provides a feasible bonding process for COF packages onto heat sinks.
Originality/value
– This study provides a soldering process for the COF LED packages. The thermal performance of the LED light source was improved significantly by the new process.@en