This article presents the design and implementation of a compact CMOS RC frequency reference. It consists of a frequency-locked loop (FLL) that locks the period of a voltage-controlled oscillator (VCO) to the time an RC network takes to charge to a reference voltage. Conventionally, an RC time constant with a near-zero temperature coefficient (TC) is realized by using a trimmed network of resistors with different TCs. In this work, such a network is used to realize a temperature-dependent reference voltage whose TC cancels that of a single-resistor RC time constant. Compared with the conventional approach, which requires resistors with TCs of opposite polarity, the proposed approach can be implemented with resistors with TCs of similar polarity, and so it can be implemented in most CMOS processes. To compensate for RC spread, a trimmed capacitor is used to adjust the nominal frequency. Two prototype chips were made, one based on p- /n-polysilicon resistors and other based on silicided/p-diffusion resistors. Fabricated in a standard 180-nm CMOS technology, the polysilicon-based prototype has an active area of 0.01 mm2 and an absolute inaccuracy of ±2800 ppm from -45 °C to 125 °C with a fixed TC-trim and a one-point frequency trim. After one week of accelerated aging at 150 °C, however, significant drift (5000 ppm) was observed. The diffusion-based prototype exhibits greater inaccuracy (±14 400 ppm) but much less drift (600 ppm).

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CMOS frequency references based on RC oscillators are usually preferred over bulky crystals in loT applications [1-5]. However, due to the process spread and finite temperature coefficient (TC) of most on-chip resistors, RC oscillators require trimming and temperature compensation to achieve decent accuracy. Enabled by high-resolution trimming techniques such as DeltaSigma [1], [2] or pulse-density [3] modulation, recent designs can obtain good accuracy (<0.1 %) at the expense of large chip area. However, existing compact (<0.02mm2) designs suffer from frequency errors in the order of 1% or more [4], [5]. Moreover, their temperature compensation schemes usually require the use of resistors with complementary TCs, which are not available in all CMOS technologies.

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Recently, rapid strides have been made in improving the accuracy of RC-based frequency references [1 -3]. Inaccuracies better than \pm 500ppm from -45^{\circ}C to 85^{\circ}C have been achieved, but typically at the expense of a costly and time-consuming 2-point trim to compensate for RC spread and temperature dependence. This paper describes a 16MHz RC-based frequency reference that achieves \pm 400ppm inaccuracy over the industrial temperature range with a single room-temperature (RT) trim. The prototype draws 88\muA from a1.8V supply and occupies 0.14mm^{2}, which represents a 2\times improvement in both power and area compared to the state of the art [2].

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This paper presents a continuous-time integrated readout interface for inertial sensors with high energy efficiency and high resolution. A dual digital-to-analog conversion (dual DAC) scheme is proposed which reduces the large DC baseline capacitance while preserving a high gain in the capacitance-to-voltage converter (CVC). A continuous-time delta-sigma modulator (CTΔΣM) is used to digitize the output signal of the CVC without kT/C noise. This results in a precision capacitive readout IC with a 5.5aF resolution in 0.5ms conversion time. It consumes 1.8mW. An inertial sensing system, consisting of the readout IC and a MEMS inertial sensor, achieves a resolution of 17.02ng/√Hz.@en

Recent years have witnessed an improvement in the energy efficiency of capacitive sensor interfaces by more than three orders of magnitude. This article reviews the architectural and circuit innovations that have contributed to this progress. The fundamental limit on the energy consumption of capacitive sensor interfaces is discussed, as well as the widely used figure-of-merit (FoM). Interfaces based on period modulation feature simple circuitry, but their power efficiency at higher resolution deteriorates. Those employing &Delta; &Sigma; modulation achieve high resolution with improved efficiency but require operational transconductance amplifiers that do not easily scale with process and supply voltage. Interfaces using successive approximation techniques feature mostly digital circuitry achieving good power efficiency at medium resolution. To achieve higher resolution, they can also be employed as the front-end in a hybrid architecture, where a back-end based on &Delta; &Sigma; modulation or a voltage-controlled oscillator (VCO) performs a fine measurement on the front-end's residue, resulting in high resolution and excellent energy efficiency simultaneously.

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This article describes a high-performance capacitance-to-digital converter (CDC) for sub-nm displacement sensing with an electrically floating target. Intended to be integrated into a displacement sensor probe, the CDC consumes only 560μW. It achieves 98.5-dB SNR in a 1-ms conversion time. With a sensing O 8-mm probe and a 25μm stand-off distance from the target, it achieves 0.18-nm resolution. Moreover, it offers an in-band common-mode rejection ratio (CMRR) higher than 117 dB, providing decent electric field interference immunity.

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This Ph.D. dissertation describes the design and realization of energy efficient readout integrated circuits (ROICs), that have an input referred noise density < 5 nV/√Hz and a linearity of < 30 ppm, as required by Wheatstone bridge sensors used in precision mechatronic systems. Novel techniques were developed, at both the system-level and circuit-level, to improve the ROIC’s energy-efficiency, while preserving its stability and precision. Two prototypes are presented, each with bestin- class energy efficiency, to demonstrate the effectiveness of the proposed techniques. @en

This paper presents a readout IC that uses an asynchronous capacitance-to-digital-converter (CDC) to digitize the capacitance of a touch sensor. A power-efficient tracking algorithm ensures that the CDC consumes negligible power consumption in the absence of touch events. To facilitate its use in wake-on-touch applications, the CDC can be periodically triggered by a co-integrated ultra-low-power relaxation oscillator. At a 38-Hz scan rate, the readout IC consumes 15 nW per touch sensor, which is the lowest reported to date.

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Commercially available gravimeters and seismometers can be used for measuring Earth’s acceleration at resolution levels in the order of ng∕Hz (where g represents earth’s gravity) but they are typically high-cost and bulky. In this work the design of a bulk micromachined MEMS device exploiting non-linear buckling behaviour is described, aiming for ng∕Hz resolution by maximising mechanical and capacitive sensitivity. High mechanical sensitivity is obtained through low structural stiffness. Near-zero stiffness is achieved through geometric design and large deformation into a region where the mechanism is statically balanced or neutrally stable. Moreover, the device has an integrated capacitive comb transducer and makes use of a high-resolution impedance readout ASIC. The sensitivity from displacement to a change in capacitance was maximised within the design and process boundaries given, by making use of a trench isolation technique and exploiting the large-displacement behaviour of the device. The measurement results demonstrate that the resonance frequency can be tuned from 8.7 Hz–18.7 Hz, depending on the process parameters and the tilt of the device. In this system, which combines an integrated capacitive transducer with a sensitivity of 2.55 aF/nm and an impedance readout chip, the theoretically achievable system resolution equals 17.02 ng∕Hz. The small size of the device and the use of integrated readout electronics allow for a wide range of practical applications for data collection aimed at the internet of things.@en

This paper describes an energy-efficient bridge readout IC (ROIC), which consists of a capacitively coupled instrumentation amplifier (CCIA) that drives a continuous-time delta–sigma modulator (CTM). By exploiting the CCIA’s ability
to block dc common-mode voltages, the bridge’s bias voltage may exceed the ROIC’s supply voltage, allowing these voltages to be independently optimized. Since bridge output is typically much smaller than bridge offset, a digital to analog converter (DAC) is used to compensate this offset before amplification and
thus increase the CCIA’s useful dynamic range. Bridge loading is reduced by using a dual-path positive feedback scheme to boost the CCIA’s input impedance. Furthermore, the CCIA’s output is gated to avoid digitizing its output spikes, which would otherwise limit the ROIC’s linearity and stability. The ROIC achieves an input-referred noise density of 3.7 nV/Hz, a noise efficiency factor (NEF) of 5, and a power efficiency factor (PEF) of 44, which both represent the state of the art. A pressure sensing system, built with the ROIC and a differential pressure sensor (AC4010), achieves 10.1-mPa (1) resolution in a 0.5-ms conversion time. The ROIC dissipates about 30% of the system’s power dissipation and contributes about 6% of its noise power. To reduce the sensor’s offset drift, a temperature compensation scheme based on an external reference resistor is used. After a two-point calibration, this scheme reduces bridge offset drift by 80× over a 50 °C range.

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This paper presents a readout IC that uses an asynchronous charge-redistribution-based capacitance-to-digital-converter (CDC) to digitize the capacitance of a touch sensor. Thanks to the power efficient tracking algorithm, the CDC consumes negligible power consumption in the absence of touch events. To facilitate stand-alone or wake-on-touch applications, the CDC can be periodically triggered by a co-integrated ultra-low power relaxation oscillator. At a 38 Hz scan-rate, the readout IC consumes 15 nW per touch sensor, which is the lowest reported to date.

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This paper describes a high-performance Capacitance-to-Digital Converter (CDC) for sub-nm displacement sensing with an electrically floating target. Intended to be integrated into a displacement sensor probe, the CDC consumes only 560μW. It achieves 98.5dB SNR in a 1ms conversion time, which is 34 times more energy-efficient than the prior art. Moreover, it also offers a 117dB in-band (1kHz) Common-mode Rejection Ratio (CMRR), providing decent electric field interference immunity.

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This paper presents an overview of energy-efficient analog-to-digital converters (ADCs) specifically intended for the readout of Wheatstone bridge sensors. Apart from achieving good energy-efficiency, such bridge-to-digital converters (BDCs) must achieve low input-referred offset, drift and noise; high gain accuracy, stability and linearity; as well as high immunity to power-supply and common-mode variations. Various BDC architectures are discussed, beginning with traditional designs, in which an instrumentation amplifier is used to drive an ADC, and moving on to more recent work, which attempt to increase energy efficiency and reduce complexity by eliminating the instrumentation amplifier. The performance of these topologies, and in particular their energy-efficiency, will be compared and summarized.

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When chopping is applied to a continuous-time sigmadelta modulator (CTΣΔM), quantization noise fold-back often occurs, leading to increased in-band noise. This can be prevented by employing a return-to-zero (RZ) digital-to-analog converter (RZ DAC) in the modulator's feedback path and arranging the chopping transitions to coincide with its RZ phases. In this letter, this technique has been extended and implemented in an energy-efficient CTΣΔM intended for the readout of Wheatstone bridge sensors. To achieve a wide common-mode input range, the modulator's summing node is implemented as an embedded capacitively coupled instrumentation amplifier which can be readily combined with a highly linear 1-bit capacitive RZ DAC. Measurements show that the proposed chopping scheme does not suffer from quantization noise fold-back and also allows a flexible choice of chopping frequency. When chopped at one-tenth of the sampling frequency, the modulator achieves 15 ppm INL, 4.5 nV/√Hz input-referred noise and a state-of-the-art noise efficiency factor of 6.1.@en

This paper presents a direct digital converter for Wheatstone bridge sensors, which is realized with commercial off-the-shelf components. The power efficiency of the readout is enhanced by embedding the bridge sensor in a second-order continuous-time sigma-delta modulator (CTDeltaSigmaM). By directly digitizing the output signal of a Wheatstone bridge in the current mode, the noise performance is dominated by the operational amplifier in the first integrator and the bridge sensor. To demonstrate the performance of the proposed circuit, an MEMS piezoresistive differential pressure sensor is used. Measurement results show that a resolution of 12.7 mParms (0.41 mOhmrms), with a 0.5-ms conversion time, can be achieved. Powered by 5 V, the circuit and the bridge sensor draw 9.55 and 7.58 mW, respectively.@en

This paper describes a low power and low noise circuit for resistive Wheatstone bridge sensor readout. The proposed readout exploits the bridge configuration of the sensor by embedding it into a second-order continuous-time sigma delta modulator (RC CTΔΣM). By directly digitizing the output signal of a Wheatstone bridge in the current mode, the noise performance is dominated by the operational transconductance amplifier (OTA) in the first integrator. The proposed readout is designed in a 0.35 μm CMOS technology. Simulation results show that it achieves an input referred noise power spectral density (PSD) of 4.2 nV/√Hz with a current consumption of 860 μA from a 5 V voltage supply. This represents a noise efficiency factor (NEF) of 4.7.@en

This paper presents the most energy-efficient CMOS temperature sensor ever reported, with a resolution FoM of 49fJ·K2, 2.7× better than the state-of-the-art. It consists of a Wheatstone bridge made from poly-silicon resistors, which is readout by a 2nd-order Continuous-Time Delta-Sigma modulator (CTDSM). This approach leads to a high resolution (160μK in 10ms) and a low supply-voltage sensitivity (< 20mK/V at room temperature).@en

This paper discusses the use of chopping in continuous-time sigma-delta modulators where 1/f noise and offset need to be suppressed by continuous-time methods. An intuitive analysis of the artifacts related to chopping is presented. Aliasing of quantization noise is found to be the main problem, especially for chopping frequencies lower than the modulator's sampling frequency (fs). Correctly timed return-to-zero and switched-capacitor DACs are proposed as a solution to the aliasing problem. In both cases, the key idea is to synchronize DAC transitions with moments when the quantization noise at the input of the first integrator is low. Circuit level simulations are presented to validate the proposed techniques.@en

Wheatstone bridge sensors are often used in precision instrumentation and measurement systems, e.g., for μK-resolution temperature sensing in wafer steppers [1] and mPa-resolution differential pressure sensing in precision air gauges [2]. Since they output small differential signals superimposed on a large common-mode (CM) voltage, typical bridge readout ICs (ROICs) consist of an instrumentation amplifier (IA) followed by an ADC [1]. This paper describes a low-noise energy-efficient ROIC, which achieves a 3.7nV/√Hz input-referred noise PSD and a power efficiency factor (PEF) of 44.1. The latter represents a 5× improvement on the state of the art [3].

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