This thesis describes the analysis, design, prototype implementation, and measurement results of high-performance Class-D amplifiers (CDAs) for audio applications.@en

This paper presents a Class-D piezoelectric speaker driver that employs a quadrature feedback chopping scheme (QCS). Compared to a conventional single feedback chopping scheme (SCS), the use of QCS can eliminate the timing skew between low-voltage (LV) and high-voltage (HV) choppers, greatly improving large-signal linearity. A prototype implemented in a 180nm BCD process achieves a peak THD+N of 88dB/-92.5dB for a 1kHz/6kHz input frequency and 37μ VR MS output noise (A-weighted) while driving a 4μ F load. Thanks to QCS, the large-signal THD+N has been improved by 29 dB, while the output voltage swing achieving -60dB THD+N has been extended from 86.9% to 99.5% of the full-scale (FS).

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This article presents a digital-input class-D amplifier (CDA) achieving high dynamic range (DR) by employing a chopped capacitive feedback network and a capacitive digital-to-analog converter (DAC). Compared with conventional resistive-feedback CDAs driven by resistive or current-steering DACs, the proposed architecture eliminates the noise from the DAC and feedback resistors. Intermodulation between the chopping, pulsewidth modulation (PWM), and DAC sampling frequency is analyzed to avoid negative impacts on the DR and linearity. Real-time dynamic element matching (RTDEM) is employed to address distortion due to mismatch in the DAC, while its intersymbol interference (ISI) is eliminated by deadbanding. The prototype, implemented in a 180-nm bipolar, CMOS, and DMOS (BCD) process, achieves 120.9 dB of DR and a peak total harmonic distortion plus noise (THD+N) of-111.2 dB. It can drive a maximum of 15/26 W into an 8-/4-Ω load with a peak efficiency of 90%/86%.

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Class-D amplifiers (CDAs) are widely used in audio applications where a high power efficiency is required. As most audio sources are digital nowadays, implementing digital-input CDAs results in higher levels of integration and lower cost. However, prior open-loop digital-input CDAs suffer from high jitter sensitivity and output-stage distortion. In [1], jitter sensitivity at small signal levels is mitigated using a buck-boost converter that adaptively lowers the supply at the expense of extra external components and reduced power efficiency. Prior closed-loop digital-input CDAs employing multi-bit current-steering [2] or resistive [3] DACs are less sensitive to jitter, but their DR is limited to about 115dB. DAC non-idealities and intermodulation distortion are also challenges, and prior works only achieved a peak textTHD+N of about -98textdB [2], [3]. This paper presents a digital-input CDA that achieves high DR by combining a low-noise capacitive DAC (CDAC) with dedicated techniques to mitigate DAC mismatch, lSI, and intermodulation distortion. A prototype implemented in a 0.18mum BCD process achieves 120.9dB DR and -111.2textdB peak textTHD+N. Furthermore, it can deliver 13W/23W at 10% THD into an 8Omega/4Omega load with a 90%/86% efficiency.

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Silicon MOSFETs-based medium-power (< 50W) Class-D amplifiers (CDAs) switching in the MHz range have gained popularity in recent years, which achieves better linearity thanks to a higher loop gain in the audio band while enabling the use of LC filters with higher cut-off frequencies. However, for high-power (>100 W) CDAs, such switching frequency and high load current could lead to significant power loss. Furthermore, in the presence of a large current and voltage applied to the load, the linearity of the system can quickly degrade due to LC filter component voltage/current dependency. Without any LC filter nonlinearity compensation technique, LC components with high voltage/current rating must be used to reach high system linearity, which are often expensive and bulky. This paper presents a CDA using a GaN-based output stage to achieve high switching frequency and good efficiency simultaneously, and an integrated controller implemented in a 180nm CMOS technology to compensate for the LC filter nonlinearity. Switching at 1.8 MHz, the CDA can deliver a maximum of 155W from a 50V supply into a $4\Omega$ load with a peak efficiency of 91.7%. It achieves a peak THD+N of −95.6 dB (0.0017%) while allowing the use of cheaper and smaller nonlinear LC components.@en

Class-D amplifiers (CDAs) are often used in audio applications due to their superior power efficiency. Due to the sensitivity of the human ear, a large dynamic range (DR) is desired, and audio DACs with up to 130dB DR are commercially available [1]. However, the DR of the CDAs they drive is typically much lower [2]-[4], mainly due to the thermal noise introduced by the input resistors of their resistive feedback networks. Reducing this resistance is difficult, as it reduces the CDA's input impedance and increases the required loop-filter capacitance. Alternatively, the CDA could be configured as a capacitively coupled chopper amplifier (CCCA), whose capacitive feedback network could then achieve low noise without reducing input impedance. However, the large PWM component present at its output would then saturate its input stage. By exploiting the inherent PWM filtering present in a feedback-after-LC architecture, this paper presents a capacitively coupled chopper CDA, resulting in significantly improved DR and THD+N. The prototype achieves 8V_RMS of integrated output noise (A-weighted), a 121.4dB DR, and -1 09.8dB THD+N while delivering a maximum of 15/26W into an 8/4Omega load with 93%/88% efficiency.

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Class-D audio amplifiers produce electromagnetic interference (EMI), which often needs to be suppressed by an external LC filter. However, due to component nonlinearity, this filter can itself cause significant distortion. This article presents a class-D amplifier that suppresses LC filter nonlinearity by 49 dB and is robust to ±30% variations in its cutoff frequency. This is achieved by a dual-loop architecture, in which an inner loop provides stability, while an outer loop provides the high gain needed to suppress the LC filter and output-stage nonlinearity. A prototype, implemented in a 180-nm BCD process, achieves -121.5-dB total harmonic distortion (THD) and -107.1-dB THD+N, which is maintained to within 3 dB even as the LC filter cutoff frequency is varied from 62 to 106 kHz. It can deliver a maximum of 21 W into a 4-Ω load with 87% efficiency and 12 W into an 8-Ω load with 91% efficiency, measured at 10% THD.

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The power supply rejection ratio (PSRR) of conventional differential closed-loop Class-D amplifiers is limited by the feedback and input resistor mismatch and finite common-mode rejection ratio (CMRR) of the operational transconductance amplifier (OTA) in the first integrator. This article presents a 14.4-V Class-D amplifier employing chopping to tackle the mismatch, thereby improving the PSRR. However, chopping-induced intermodulation (IM) within a pulsewidth modulation (PWM)-based Class-D amplifier can severely degrade PSRR and linearity. Techniques to mitigate such IM are proposed and analyzed. To chop the 14.4-V PWM output signal, a high-voltage (HV) chopper employing double-diffused MOS (DMOS) transistors is developed. Its timing is carefully aligned with that of the low-voltage (LV) choppers to avoid further linearity degradation. The prototype, fabricated in a 180-nm BCD process, achieves a PSRR of >110 dB at low frequencies, which remains above 79 dB up to 20 kHz. It achieves a total harmonic distortion (THD) of -109.1 dB and can deliver a maximum of 14 W into an 8- \Omega load with 93% efficiency while occupying a silicon area of 5 mm2.

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This article presents a class-D amplifier (CDA) with high dynamic range (DR). To eliminate the typically dominant noise contribution of a resistive feedback network, the input and feedback signals are chopped and applied to a capacitive feedback network. However, this leads to high-voltage (HV) transients at the input of the loop filter, which, due to timing and impedance mismatch in the chopped feedback network, could degrade linearity and even overstress low-voltage (LV) core devices. Robust processing of the HV chopped feedback signal is guaranteed with chopper timing skew correction, chopper impedance matching, and deadbanding. The prototype, implemented in a 180-nm bipolar-CMOS-DMOS (BCD) process, achieves 121.4 dB of DR, 5.9 dB higher than state-of-the-art closed-loop CDAs, and 8-μVRMS output-referred noise (A-weighted). It also achieves a peak total harmonic distortion (THD) + N of -109.8 dB and a peak efficiency of 93%/88% while driving 15 W/26 W into an 8-4-Ω load.

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This article presents a fully dynamic scalable switched-capacitor delta-sigma modulator that achieves a 94.1-dB dynamic range (DR). Power-and- bandwidth scalability by only changing the clock frequency is achieved using a capacitively biased and swing-enhanced floating inverter operational transconductance amplifier (OTA). Fabricated in a 180-nm CMOS process, the prototype achieves an signal-to-noise-and-distortion ratio (SNDR) of >87 dB across 4× scaling from 100 to 400 kHz of the sampling frequency f_ S. At 200-kHz f_ S , it achieves an SNDR/DR of 89.3/94.1 dB while consuming 4 μ W , leading to a DR-based Schreier figure of merit (FoM) of 177.1 dB.

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Recent years have witnessed an improvement in the energy efficiency of capacitive sensor interfaces by more than three orders of magnitude. This article reviews the architectural and circuit innovations that have contributed to this progress. The fundamental limit on the energy consumption of capacitive sensor interfaces is discussed, as well as the widely used figure-of-merit (FoM). Interfaces based on period modulation feature simple circuitry, but their power efficiency at higher resolution deteriorates. Those employing &Delta; &Sigma; modulation achieve high resolution with improved efficiency but require operational transconductance amplifiers that do not easily scale with process and supply voltage. Interfaces using successive approximation techniques feature mostly digital circuitry achieving good power efficiency at medium resolution. To achieve higher resolution, they can also be employed as the front-end in a hybrid architecture, where a back-end based on &Delta; &Sigma; modulation or a voltage-controlled oscillator (VCO) performs a fine measurement on the front-end's residue, resulting in high resolution and excellent energy efficiency simultaneously.

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This paper reports a chopper Class-D audio amplifier that obtains high PSRR over the entire audio band. A chopping scheme is proposed to minimize intermodulation distortion between pulse-width modulation (PWM) and chopping in the audio band. A high-voltage chopper is developed to handle a 14.4 V PWM signal. Timing matching techniques are proposed to minimize chopping nonidealities which ensure good PSRR and THD. Fabricated in a 180nm BCD process, the prototype obtains a PSRR >109 dB at 217 Hz and >83.7 dB over the entire audio band. It also achieves -109.1 dB/-98 dB THD/THD+N and can deliver a maximum of 13 W to an 8-Ω load.@en

This paper reports a Class-D audio amplifier that uses multiloop feedback to suppress output LC filter nonlinearity by 49 dB, enabling the use of small, low-cost LC filters with ±30% spread while maintaining low distortion. Fabricated in a 180 nm BCD process, the prototype achieves a THD of-121.5 dB and a THD+N of-107.1 dB. It delivers 12W/21W into an 8-Ω/4-Ω load with 91%/87% efficiency.

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IoT sensing applications operating from batteries or harvested energy require microwatt data converters. To accurately measure small signals, they often need to achieve a high DR (>90dB) and better linearity than the transducers themselves (>14b) with a BW in the kHz range. IoT systems also often consist of multiple sensing modalities with different BW requirements and are often heavily duty-cycled to reduce power consumption. This paper presents a fully dynamic discrete-time delta-sigma modulator (DTDSM) that supports 4x bandwidth/power scaling without any programming overhead except for changing fs, using a capacitively biased swing-enhanced floating inverter amplifier (SEFIA). The prototype, fabricated in 180nm CMOS, consumes only 4μW at 800Hz BW and achieves >87dB SNDR over 2 octaves of fs, between 100 kHz and 400 kHz, and a DR of 94.1 dB while operating with an OSR of 125.

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This article presents a 28-W class-D amplifier for automotive applications. The combination of a high switching frequency and a hybrid multibit Δ Σ M-PWM scheme results in high linearity over a wide range of output power, as well as low AM-band EMI. As a result, only a small (150-kHz cutoff frequency), and thus low-cost, LC filter is needed to meet the CISPR-25 EMI average limit (150 kHz-30 MHz) with 10-dB margin. At 28-W output power, the proposed amplifier achieves 91% efficiency while driving a 4- Ω load from a 14.4-V supply. It attains a peak THD+N of 0.00077% (-102.2 dB) for a 1-kHz input signal.

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This paper describes a class-D audio amplifier with a multilevel output stage that reduces both EMI and idle power. High loop gain, and thus high linearity, are enabled by a relatively high (4.2 MHz) switching frequency, which relaxes the requirements on its output LC filter. Fabricated in a 180nm BCD technology, it can drive 14 W into an 8-Ω load with state-of-the-art performance: -107.8 dB THD+N, 91% peak efficiency, and 7 mA quiescent current. It meets the CISPR 25 Class 5 radiated emission standard with a low-cost 580 kHz LC filter, improving the state-of-the-art by 5.8x.

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This article presents a Class-D audio amplifier for automotive applications. Low electromagnetic interference (EMI) and, hence, smaller LC filter size are obtained by employing a fully differential multilevel output stage switching at 4.2 MHz. A modulation scheme with minimal switching activity at zero input reduces idle power, which is further assisted by a gate-charge reuse scheme. It also achieves high linearity due to the high loop gain realized by a third-order feedback loop with a bandwidth of 800 kHz. The prototype, fabricated in a 180-nm high-voltage BCD process, achieves a minimum THD+N of -107.8 dB/-102 dB and a peak efficiency of 91%/87% with 8- and 4-Ω loads, respectively, while drawing 7-mA quiescent current from a 14.4-V supply. The prototype meets the CISPR 25 Class 5 EMI standard with a 5.7-dB margin using an LC filter with a cutoff frequency of 580 kHz.

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Class-D amplifiers are often used in high-power audio applications due to their high power efficiency. They typically employ pulse-width modulation (PWM) at a fixed carrier frequency, which may cause electromagnetic interference (EMI). Setting this frequency f_PWM) below the AM band (535 to 1605kHz) helps mitigate this, but its harmonics still contain substantial energy and must be filtered out by bulky LC filters with low cut-off frequencies (f_c = 20 to 40 kHz), significantly increasing system cost and size. Stability considerations also constrain the amplifier's unity-gain frequency to be < mathrm{f} {mathrm{PWM}}/pi [1], compromising the audio-band loop gain required to suppress output-stage nonlinearity. Setting f_PWM above the AM band helps increase f_c and allows a higher loop gain [2]. However, this results in narrower pulses at higher power levels (higher modulation index), which cannot be faithfully produced by the output stage, thus exacerbating its non-linearity. Delta-sigma modulation (DeltaSigma M) has fixed pulse widths and does not suffer from these narrow-pulse artefacts. However, the out-of-band noise of 1bit modulators then requires larger LC filters. Moreover, high-order loop filters must be used to achieve sufficient SQNR, which then require additional techniques to maintain stability as the modulation range approaches 100% [3].

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