High-power white light-emitting diodes (LEDs) have demonstrated superior efficiency and reliability compared to traditional white light sources. However, ensuring maximum performance for a prolonged lifetime use presents a significant challenge for manufacturers and end users, especially in safety–critical applications. Thus, identifying functional anomalies and predicting the remaining useful lifetime (RUL) is of enormous importance in the operational longevity of the device. To address such challenges, this study proposes a combination of distance-based Mahalanobis distance (MD), entropy generation rate (EGR), and deep learning models for improved anomaly detection and RUL prediction accuracy. Unlike conventional health indicators based on luminous flux data that are challenging to monitor relevant optical performance, the MD and EGR methods are employed to extract in-situ monitored thermal and electrical data as new health indicators. Long short-term memory recurrent neural networks (LSTM-RNN) and convolutional neural networks (CNN) are established to detect anomalies and predict the RUL. The accelerated degradation tests of 3 W high-power white LED have been conducted, and the online and offline collected experimental data are deployed for model development and performance evaluation. The performance of the proposed methods is compared against the Illuminating Engineering Society of North America (IESNA) TM-21 method. The results indicate that LSTM-RNN, when combined with either MD or EGR, can detect anomalies with significantly fewer data (70 %) than is typically required. Furthermore, a significant improvement in prediction accuracy in RUL prediction based on MD and EGR-constructed time series health indicators and employed with the LSTM-RNN model demonstrates the effectiveness of the proposed methods.

As the next generation of semiconductor devices, SiC MOSFETs have demonstrated significant performance improvements in switching loss, switching frequency, and high-temperature operation compared to Si-based MOSFETs. However, the long-term reliability of such devices and their packaging continues to be a major concern. Towards addressing this challenge, this study proposes a multi-objective optimization design method for parasitic inductance (L), thermal strain (?), and thermal resistance (R) of SiC MOSFETs with Fan-Out Panel-Level Packaging (FOPLP). First, the orthogonal experimental design was employed to investigate the thickness effects of baseplate, solder, die and redistribution layer (RDL) on L, e, and R. Then, the multi-objective optimization was developed to simultaneously reduce L, G, and R. Finally the fatigue lifetimes of the optimized and initial SiC MOSFET FOPLP structures were compared to verify the optimization's accuracy. Study findings include: (1) Solder thickness was the most significant influence factor for L, e and R of SiC MOSFET FOPLP, L and R increased, and e decreased with increasing solder thickness; (2) The proposed multi-objective optimization method coupled with a genetic algorithm achieved 14.79, 8.96, and 9.28% reduction of L, e, and R, respectively; (3) The fatigue lifetime of solder (SAC305) was evaluated using the Coffin-Manson model, with predicted lifetimes before and after optimization being 6786 and 7085 cycles, respectively, demonstrating that the proposed approach significantly enhanced the designed SiC MOSFET FOPLP's long-term thermal cycling reliability.

SiC MOSFET is mainly characterized by the higher electric breakdown field, higher thermal conductivity, and lower switching loss enabling high breakdown voltage, high-temperature operation, and high switching frequency. However, their performances are considerably limited by the high parasitic inductance and poor heat dissipation capabilities associated with existing wire-bonding packaging methods. To address this challenge, a 1200 V/136 A fan-out panel-level packaging (FOPLP) SiC MOSFET with a size of $8\times {8} \times {0}.{75}$ mm was proposed. The electrical parameters of the devices were characterized experimentally. Both the static and dynamic parameters of the package matched the bare die values, which confirmed the functioning of the proposed packaging method for SiC MOSFET. The package parasitic inductance, thermal resistance, and soldering stress were analyzed through simulations. The reliability of the packages was evaluated by performing the thermal cycling test. The experimental results revealed that: 1) SiC MOSFET FOPLP had 0.36 nH drain-source parasitic inductance at 100 kHz, a 96% reduction compared with a conventional wire-bonded package; 2) double-sided cooling enabled the packages to exhibit a thermal resistance as low as 0.55 °C/W; and 3) after 2000 thermal cycling cycles, drain-source ON-state resistance [RDS(on)] increased by less than 2%, which revealed the higher reliability of the package under thermal cycling.

Considerable advancements in power semiconductor devices have resulted in such devices being increasingly adopted in applications of energy generation, conversion, and transmission. Hence, we proposed a fan-out panel-level packaging (FOPLP) design for 30-V Si-based metal-oxide-semiconductor field-effect transistor (MOSFET). To achieve superior reliability of packaging, we applied the nondominated sorting genetic algorithm with elitist strategy (NSGA-II) and ant colony optimization-backpropagation neural network (ACO-BPNN) to optimize the design of redistribution layer (RDL) in FOPLP. We first quantified the thermal resistance and thermomechanical coupling stress of the designed package under thermal cycling loading. Next, NSGA-II and ACO-BPNN were used to optimize the size of the RDL blind via. Finally, the effectiveness of the proposed reliability optimization methods was verified by performing thermal shock reliability aging tests on the prepared devices.