Optimization of heterojunction c-Si solar cells with front junction architecture

Abstract

Wafer-based crystalline silicon (c-Si) solar cells currently dominate the photovoltaic (PV) market with high-thermal budget (T > 700 ∘C) architectures (e.g. i-PERC and PERT). However, also low-thermal (T < 250 ∘C) budget heterojunction architecture holds the potential to become mainstream owing to the achievable high efficiency and the relatively simple lithography-free process. A typical heterojunction c-Si solar cell is indeed based on textured n-type and high bulk lifetime wafer. Its front and rear sides are passivated with less than 10-nm thick intrinsic (i) hydrogenated amorphous silicon (a-Si:H) and front and rear side coated with less than 10-nm thick doped a-Si:H layers. Finally, transparent conductive oxide (TCO) and metal at both front and rear side terminate the device. Of course, the front side metal is merely a grid, allowing light to impinge on the c-Si wafer. In this project, an HIT heterojunction architecture is investigated, it is used a double intrinsic passivating layer at the front and an highly hydrogenated (p) a-Si:H forming the emitter; i/n passivating stack at the rear in the role of back surface field; a TCO formed by IO:H and ITO and finally copper as front metal contact.