This thesis focuses on the design and optimization of Successive-approximation (SAR) Analog-to-Digital Converter (ADC), with a primary focus on enhancing the Bit Error Rate (BER). SAR ADCs are widely used in various applications due to their power-efficient characteristics. The critical point addressed in this research is improving the BER of synchronous SAR ADCs without the necessity to reduce the sampling speed...

Transmit digital-to-analog converters have become an essential building block for state-of-the-art Ethernet infrastructures. They are also one of the most significant sources of power consumption in an Ethernet physical layer (PHY) transceiver. These devices must maintain high linearity and a well-defined impedance of 100 Ω while operating at a speed of several GS/s. This thesis investigates the resistive digital-to-analog converter architecture, which is inherently more power-efficient than the widely used current-steering architecture. A technique to linearize the supply current, which reduces distortion caused by finite supply impedance, is proposed. The resulting 12-bit DAC designed in 180nm technology maintains INL and DNL error of +-0.6 LSB on a 12-bit level across temperature (-40 to 150°C) and corners. The DAC operates with a clock speed of 200 MS/s, achieving IM3 >85 dB at low frequency.