Board level reliability can be of high interest for automotive electronic components when exposed to vibration-prone environments. However, the absence of an industry standard for board level vibration testing poses several challenges in establishing a well-characterized test setup. One of the challenges is that automotive applications can induce abnormal stresses on components that can lead to early failures in the field. Such loading conditions are not always covered in the current board level vibration test methods. This paper aims to correlate the stresses from automotive modules to board levels by measuring the printed circuit board (PCB) vibration spectrum. Firstly, the study compares and assesses several module board level vibration measurement units, such as LASER Doppler Vibrometer (LDV), strain gauges, and accelerometers. Experiments and simulations show that LDV enables good correlation with Micro-electro Mechanical Systems (MEMS) accelerometers. Secondly, the module-board interaction unveils insights into several module design features that impact the PCB vibration response and solder joint interconnect reliability. These findings underscore the necessity for the user to correctly validate the reliability of packages beyond board level testing, i.e., at the module level. This reliability test approach enables the translation of reliability test results from the lab to the field life of components once built in the final application equipment.

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The objective of this work is to develop a microstructure-based simulation approach to assess the fatigue life of solder joints that are used by the microelectronics industry. The developed approach can generate solder joints with random grain morphologies by means of 3D Voronoi tessellation. The anisotropic material behavior of each grain is described by the Garofalo creep equation combined with Hill's definition of the equivalent stress for anisotropic materials. Grain boundaries are implemented as interface elements, with an isotropic creep constitutive model. The stochastic variability in the creep response of solder joints was qualitatively estimated by generating 100 unique solder joints containing 5 to 9 grains, each having a random material orientation. These joints were independently loaded with a realistic stress level for microelectronic products during thermal cycling. The volume-averaged creep strain energy density in the solder joints was used to predict the fatigue life of the solder joints. The results showed a factor of ~4 difference in expected lifetime of the individual solder joints. Next, nine randomly picked solder joints from the above-mentioned pool of 100 were sandwiched between a silicon die and a printed circuit board to form a simulation model of a Wafer-Level Chip-Scale package (WLCSP). The creep strain energy density in the joints was computed for 34 unique cases of the WLCSP. A factor of ~2.5 between the highest and lowest estimate for the solder joint life was found. The slope of the corresponding Weibull distribution equals ~6, which falls within the slopes typical reported for solder joint reliability of WLCSPs.

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Solder joint failure is one of the most common board-level failure modes in electronic components. It is crucial for a next-generation reliability assessment method to have an in-situ health monitoring system in place to evaluate the current state of degradation. This is achieved by specialized embedded sensors and processing the data on the edge. This study focuses on monitoring the mechanical degradation of package-to-PCB solder interconnects of a WLCSP using a high-resolution piezoresistive sensor. First, a measurement workflow was set up to optimize and significantly improve the sensor readout time. Then, utilizing a design of experiments, the test specimens were subjected to certain combinations of mechanical and thermal loads in a four-point bending setup. Temperature-coupled mechanical loading showed a greater impact on the resulting stress pattern compared to that of a superposition of the corresponding individual purely thermal and mechanical load configurations. Finally, the specimens were tested under a purely mechanical load until failure, and a correlation between the recorded stress pattern and the initiation and propagation of a crack was established.@en

Board level vibration testing is intended to assess prediction of the reliability of solder joint interconnects that are formed between electronic components and printed circuit boards (PCB). Frailties in the stress test experiment might lead to false board level reliability (BLR) evaluations. Therefore, it is essential to have a well-characterized board level vibration test method. Currently, there is no industrial test standard that prescribes board level vibration test method for electronic components at the PCB level. This paper examines the vibration test standards that are currently available in the industry and their applicability at the solder joint interconnect level. Next to that, it surveys the state-of-the-art board level vibration test setups and their impact on PCB dynamic loading and reliability at solder joint-PCB interface. It collates research on major building blocks of a board level vibration test method that includes vibration measurement techniques, PCB assemblies under test, board mounting schemes, operating environments, fault detection systems, and vibration test stress conditions that are currently used in the domain of solder joint level vibration testing. The findings from this paper are expected to reveal pitfalls and challenges while setting up board level vibration test experiments for electronic components. In addition, this paper attempts to identify research efforts that are required to make board level vibration testing a more credible means for assessing solder joint reliability. Outcomes from this study can further be used to guide future board level vibration specifications for electronic components.

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