The use of System-on-Chip (SoC) solutions in the design of on-board data handling systems is an important step towards further miniaturization in space. However, the Total Ionizing Dose (TID) and Single Event Effects (SEE) characterization of these complex devices present new challenges that are either not fully addressed by current testing guidelines or may result in expensive, cumbersome test configurations. In this paper we report the test setups, procedures and results for TID testing of a SoC microcontroller both using standard C60o and low-energy protons beams. This paper specifically points out the differences in the test methodology and in the challenges between TID testing with proton beam and with the conventional gamma ray irradiation. New test setup and procedures are proposed which are capable of emulating typical mission conditions (clock, bias, software, reprogramming, etc.) while keeping the test setup as simple as possible at the same time.@en

This paper presents an intended test setup and methodology for testing micro-controller SoCs against the effects of ionizing radiations. The method structure is based on a modular test sequence for test definition, coding, validation and setup. It will be illustrated by the relevant example of a microcontroller solution including lockstep options. Our methodology proposes using low-energy protons for irradiation, and this paper compares this approach with current techniques, showing how proton testing is becoming increasingly interesting, especially for ultra-deep submicron processes in proton dominated environments like low-shielded Low Earth Orbit missions or aircraft avionics. Beyond the convenience of a simplified test setup one of the main advantages of the proton irradiation approach is that it can be used for simultaneous Single Event Effects (SEE) and Total Ionizing Dose (TID) characterization, closer to the "test as you fly" approach.

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This paper discusses radiation tests on complex System-on-Chip (SoC) controllers using Low-Energy Protons (LEPs). The aim of this novel set of guidelines is to be also applicable to System In Package (SIP) or hybrid components that are now often used to overcome printed circuit board's real estate restrictions in Hi-Rel electronics.

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