In this contribution, We analyze the bandwidth versus accuracy trade-offs of conventional two-step de-embedding approaches, often employed to extract the device model parameters. The accuracy limitation of incorporating the pad/line section of classical DUT test-fixtures into shunt-series complex and frequency-dependent elements is analyzed by means of linear circuit simulations and EM parametric analysis. The de-embedding accuracy is then evaluated by employing 3D surfaces to include both the frequency and the geometrical dependency. To validate the presented analysis, classical device monitoring parameters are extracted versus frequency for the same nMOS device embedded in two different fixtures. One topology only supports pad level calibration, thus including the fixture pad/line section in the de-embedding process. The second topology allows a direct on-Wafer calibration (reference plane set on metal-1 in close proximity to the DUT) thus minimizing the residual parasitics to be removed by the de-embedding step. Experimental data are then presented and compared to simulation test benches to highlight the improved consistency of the extracted model parameters of the metal-1 calibration approach up to 220GHz.@en

In this contribution, we employ direct calibration/de-embedding approaches to validate the large signal device model of state-of-the-art HBTs and CMOS technologies operating in the mm-wave frequency band WR6. The capability of placing the first tier calibration reference plane in close proximity to the DUT allows the large signal metric to be directly compared with foundry models.@en

In this contribution we present a simulation test-bench capable of separating and quantifying all the major sources of uncertainties in user-designed direct calibration/de-embedding test-fixtures. The calibrated data systematic errors arising from the different response of the standard definitions when compared to their in-fixture ones as well as the random contributions arising from the instrument noise and probe (variable) misplacement are described and propagated through the calibration equations versus frequency. Finally, the S-parameter uncertainties are further propagated to the device level parameters, i.e., gate capacitance and transducer gain to provide the required link between calibration accuracy and modelling uncertainty. Preliminary measurement data in the 140GHz-220GHz range are compared versus the uncertainty model prediction.@en

In this paper, we present a thru-reflect-line (TRL) calibration/de-embedding kit integrated in the back-end-of-line of a SiGe technology, which allows direct calibration at the first metallization layer, thus moving the reference planes as close as possible to the intrinsic device. The proposed calibration/ de-embedding kit features capacitively loaded inverted CPW lines, allowing to reduce the losses arising from the conducting (i.e., silicon) substrate, by confining the propagating field in the low-loss dielectric layers. The structures have been designed specifically for (sub) mm-wave measurements, as complementary to conventional de-embedding kits used at lower frequencies. A simplified analytical model is presented to support the design of the capacitively loaded CPW lines. Results of a calibration/de-embedding kit, realized using a 130-nm BiCMOS technology are experimentally obtained in the WR-03 waveguide band. Worst case error bounds providing error below 5% in the entire WR3 band are demonstrated. Comparison between direct calibration and de-embedding using calibration transfer from fused silica are provided to highlight the improvements of the proposed approach in the mm-wave bands. Finally, the TRL calibration kit is employed for S-parameter measurements of a heterojunction bipolar transistor and the results are compared to the HiCUM model of the same transistor for verification@en