In multi-electrode arrays (MEAs), for electrical recording and electrical stimulation, high voltage (HV) switches are employed to build an analog multiplexer to conduct either a HV stimulation signal from the pulse generator circuit to an electrode or a low-voltage noise-sensitive signal from the electrode to a recording stage. In this brief, a new circuit structure is proposed for HV switches that significantly improves their switching speed, reduces their power dissipation, and also employs a minimum number of bulky HV devices. In order to reduce the transition time of the proposed switch without consuming a large amount of power, during the transition time that the switch is turning on/off, a large current flows through the driver circuit of the switch to turn the switch on/off rapidly; however, after the transition times, this current is significantly reduced to save power. Based on the proposed HV switch, a multiplexer structure has been implemented in 25-V, 0.18- μm CMOS IC technology and the measurement results prove its efficacy. Supplied with 25 V and operating with 300 nA current consumption, this switch swings over 20 V with a relatively constant on-resistance of 100Ω and features a 80 ns transition time.

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A novel signal-specific power-efficient analog-to-digital converter (ADC) is proposed for sensorinterface applications. Instead of digitizing each analog sample independently, the proposed ADC determines the digital code corresponding to each new input sample by digitizing the difference of two consecutive samples. Therefore, for the applications with low-varying input signals, such as image sensors and ECG readouts, the difference of two consecutive samples is much smaller than the ADC full-scale range for the majority of the input samples, the power consumption of the capacitive digital-to-analog converter, the comparator, and the digital circuits of the proposed ADC is saved due to reducing the ADC activity. The prototype was fabricated using a 0.18-μm CMOS technology. Measurement results of 1 V, 8 bit, 20 kS/sADC confirm that for a 10-kHz input sine wave, the effectivenumber of bits is 7 while the power consumption of the entireADC is 1.12 μW. However, for the same sampling rate, the power consumption is only 106 nW for a low-varying 100-Hzinput sine wave.

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In this paper, a new low-energy switching technique with low common-mode voltage variation is proposed for successive-approximation analog-to-digital converters (SA-ADCs). In the proposed scheme, not only the switching energy consumed within the first three comparisons is less than zero, but also other comparisons are made with the low-power monotonic method. Therefore, the switching energy of the capacitive array, including the consumed energy during the sampling phase, is reduced by 90.68% compared with the conventional counterpart. Moreover, since the variation of the input common-mode voltage of the employed comparator is only 0.125Vref, where Vref is the reference voltage of the ADC, the required comparator’s performance can be much more relaxed leading to more power saving. Post-layout simulation results of a 10-bit 1-MS/s SA-ADC in a 0.18-µm CMOS technology show a signal-to-noise-and-distortion ratio (SNDR) of 61 dB, a spurious-free dynamic range (SFDR) of 79.8 dB, and an effective number of 9.84 bits. The ADC consumes 35.3 µW with a 1.8-V supply and achieves a Figure-of-Merit (FoM) of 38.5 fJ/conversion-step.
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Phase-domain Analog-to-Digital Converters (Ph-ADCs) have been considered for power-efficient implementation of body-area network transceivers employing phase demodulation. Conventional implementations of the Ph-ADCs, which work based on a full-flash zero-crossing algorithm, use linear resistive/current combiners to determine the thermometer digital code of the signal phase. These architectures suffer from high-accuracy requirements, high-circuit complexity, and high-power consumption. Therefore, in this paper, a new IQ-assisted binary-search algorithm is proposed for implementing the Ph-ADC. The proposed Ph-ADC architecture avoids employing the power-hungry linear combiner. Moreover, for an N-bit Ph-ADC, the proposed algorithm requires only N +1 comparisons, whereas the conventional full-flash counterpart demands 2N-1 comparisons. Based on the proposed architecture, two different 5-bit charge-redistribution Ph-ADC s are designed and one of them is fabricated in a standard 0.18-μm CMOS technology. The prototype achieves an ENOB of 4.85 bits at 1 MS/s, while dissipating 12.9 μW from a 1.2-V supply.@en

In this paper, a highly-linear CMOS transconductor for use in tracking low-pass Gm-C filters employed in digital TV tuners is proposed. In order to improve the linearity of the proposed transconductor at the wide VHF/UHF frequency bands, a new linearization technique based on parallel operation of auxiliary transconductors in triode and subthreshold regions is proposed. Based on the proposed transconductor, a third-order elliptic low-pass Gm-C filter is designed and simulated in a standard 0.18-μm CMOS technology. The cutoff frequency of the filter is tunable from 50MHz to 300 MHz. Simulation results show that the designed filter provides a maximum in-band output referred third-order intercept point of 21.5 dBm while drawing an average current of 106 mA from a supply voltage of 1.8 V.@en

This brief presents a fast and power-efficient voltage levelshifting circuit capable of converting extremely low levels of input voltages into high output voltage levels. The efficiency of the proposed circuit is due to the fact that not only the strength of the pull-up device is significantly reduced when the pull-down device is pulling down the output node, but the strength of the pull-down device is also increased using a low-power auxiliary circuit. Postlayout simulation results of the proposed circuit in a 0.18-μm technology demonstrate a total energy per transition of 157 fJ, a static power dissipation of 0.3 nW, and a propagation delay of 30 ns for input frequency of 1 MHz, low supply voltage level of VDDL = 0.4 V, and high supply voltage level of VDDH = 1.8 V.@en

In this paper a low-power audio ΣΔ modulator under 0.7 V supply is proposed. The proposed structure uses a second order modulator with cascade integrator feedback (CIFB) and half-delayed input-feedforward architectures. In order to avoid the extremely scaling the loop filter coefficients in the CIFB ΣΔ modulator with tracking quantizer, the proposed modulator employs a novel difference-tracking multi-bit quantizer. Since the maximum step size of the proposed quantizer output signal is considered 3VLSB, compared with the conventional counterpart, a larger noise transfer function (NTF) gain can be allowed leading to a considerable reduction in the complexity and power consumption of the modulator. Simulation results of the proposed modulator in a 0.18-μm CMOS technology confirm that an SNDR of 97.9 dB is achieved for a 20-kHz signal bandwidth at the cost of 400 μW power consumption when the supply voltage is only 0.7 V.@en