Digital Micromirror Device (DMD)-based grayscale lithography is a promising tool for three dimensional (3D) microstructuring of thick-film photoresist since it is a maskless process, provides possibility for the free-form of 3D microstructures, and therefore rapid and cost-effective microfabrication. However, process parameter determination lacks efficient optimization tool, and thus conventional look-up table (indicating the relationship between development depth and exposure dose value under a fixed development time) approach with manual try-and-error adjustment is still gold standard. In this paper, we firstly present a complete “input target-output parameters” single exposure optimization method for 3D microstructuring utilizing DMD-based grayscale lithography. This numerical optimization based on lithography simulation and sensitivity analysis can automatically optimize a combination of three process parameters for target microstructure; exposure dose pattern, a focal position, and development time. Through a series of experiments using a 20 μm thick positive photoresist, validity of the proposed optimization approach has been successfully verified. Secondly, with the purpose of further advancing accuracy and improve the uniformity of precision for the target area, a multiple exposure optimization method is proposed. The simulated results proved that the multiple exposure optimization method is a promising strategy to further improve precision for thicker photoresist structure.@en

We report a multiple patterning approach utilizing digital-micromirror-device (DMD)-based grayscale lithography, providing a solution to improve fabrication accuracy for entire target three-dimensional structure. Because DMD-based lithography system consists a projection lens system, better resolution can be obtained around focal position comparing to the outer region of depth of focus. Thus, for thick-film resist micro structuring, exposing with multiple focal positions with separate grayscale masks leads to improvement of fabrication accuracy. In order to find the best combination of the multiple focal positions and their grayscale masks, the computational optimization is combined to the multiple patterning approach. Through a several experiments, effectiveness of the proposed approach was successfully demonstrated.

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A low-cost temperature sensor with on-chip sigma-delta ADC and digital bus interface was realized in a 0.5 /spl mu/m CMOS process. Substrate PNP transistors are used for temperature sensing and for generating the ADC's reference voltage. To obtain a high initial accuracy in the readout circuitry, chopper amplifiers and dynamic element matching are used. High linearity is obtained by using second-order curvature correction. With these measures, the sensor's temperature error is dominated by spread on the base-emitter voltage of the PNP transistors. This is trimmed after packaging by comparing the sensor's output with the die temperature measured using an extra on-chip calibration transistor. Compared to traditional calibration techniques, this procedure is much faster and therefore reduces production costs. The sensor is accurate to within /spl plusmn/0.5/spl deg/C (3/spl sigma/) from -50/spl deg/C to 120/spl deg/C.@en