This article introduces a modular, direct time-of-flight (TOF) depth sensor. Each module is digitally synthesized and features a 2 × (8 × 8) single-photon avalanche diode (SPAD) pixel array, an edge-sensitive decision tree, a shared time-to-digital converter (TDC), 21-bit per-pixel memory, and in-locus data processing. Each module operates autonomously, by internal data acquisition, management, and storage, being periodically read out by an external access. The prototype was fabricated in a TSMC 3-D-stacked 45/65-nm CMOS technology, featuring backside illumination (BSI) SPAD detectors on the top tier, and readout circuit on the bottom tier. The sensor was characterized by single-point measurements, in two different modes of resolution and range. In low-resolution mode, a maximum of 300-m and 80-cm accuracy was recorded; on the other hand, in high-resolution mode, the maximum range and accuracy were 150 m and 7 cm, respectively. The module was also used in a flexible scanning light detection and ranging (LiDAR) system, where a 256 × 256 depth map, with millimeter precision, was obtained. A laser signature based on pulse-position modulation (PPM) is also proposed, achieving a maximum of 28-dB interference reduction.

We present the world's first backside-illuminated (BSI) single-photon avalanche diode (SPAD) based on standard silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. This SPAD achieves a good dark count rate (DCR) after backside etching, comparable to DCRs of BSI SPADs fabricated on bulk wafers. Unlike bulk-wafer-based BSI SPADs, which typically suffer from poor violet and blue sensitivity, the proposed BSI SPAD features increased near-ultraviolet sensitivity as well as significant sensitivity in the violet and blue spectral ranges, thanks to the ultrathin-body SOI. To the best of our knowledge, this is the best result ever reported for any BSI SPAD in the standard CMOS technology. In addition, it also shows high sensitivity at long wavelengths thanks to the interface between silicon and silicon-dioxide layers. Therefore, it achieves a photon detection probability over 26% at 500 nm and 10% in the 400-875 nm wavelength range at 3 V excess bias voltage. The timing jitter is 119 ps full width at half maximum at the same operation condition at 637 nm wavelength. For the proposed BSI SPAD, the buried oxide layer in SOI wafers is used as an etching stop during the wafer backside-etching process, and therefore it ensures the excellent performance uniformity in large arrays.

Silicon Photomultipliers (SiPMs), which emerged as all solid state, MRI compatible alternative to PMTs, can provide high miniaturization and increased timing performance. Large effort has been spent in improving the figures of merit of such devices (e.g. jitter, timing resolution, sensitivity, noise, etc.). In this paper we propose a novel approach relying on the combination of photonic crystals with microlens arrays, integrated on top of each SPAD cell in the SiPM, to collimate and focus the light generated by a scintillator, in order to improve the overall timing performance of the system so as to approach the 10ps target, while at the same time reducing the noise floor (Dark Count Rate).