We investigate die-level and wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions, using multiple substrates with and without through-silicon vias (TSVs). Dolan junctions fabricated on planar substrates have the highest yield and lowest room-temperature conductance spread, equivalent to ∼ 100 M H z in transmon frequency. In TSV-integrated substrates, Dolan junctions suffer most in both yield and disorder, making Manhattan junctions preferable. Manhattan junctions show pronounced conductance decrease from wafer center to edge, which we qualitatively capture using a geometric model of spatially-dependent resist shadowing during junction electrode evaporation. Analysis of actual junction overlap areas using scanning electron micrographs supports the model, and further points to a remnant spatial dependence possibly due to contact resistance.

We present the use of a set of airbridges to trim the frequency of microwave coplanar-waveguide (CPW) resonators post-fabrication. This method is compatible with the fabrication steps of conventional CPW airbridges and crossovers and increases device yield by allowing compensation of design and fabrication uncertainty with 100 MHz range and 10 MHz resolution. We showcase two applications in circuit QED. The first is the elimination of frequency collisions between resonators intended to readout different transmons by frequency-division multiplexing. The second is frequency matching of readout and Purcell-filter resonator pairs. Combining this matching with transmon frequency trimming by laser annealing reliably achieves fast and high-fidelity readout across 17-transmon quantum processors.

Minimizing leakage from computational states is a challenge when using many-level systems like superconducting quantum circuits as qubits. We realize and extend the quantum-hardware-efficient, all-microwave leakage reduction unit (LRU) for transmons in a circuit QED architecture proposed by Battistel et al. This LRU effectively reduces leakage in the second- and third-excited transmon states with up to 99% efficacy in 220 ns, with minimum impact on the qubit subspace. As a first application in the context of quantum error correction, we show how multiple simultaneous LRUs can reduce the error detection rate and suppress leakage buildup within 1% in data and ancilla qubits over 50 cycles of a weight-2 stabilizer measurement.

The preparation of thermal equilibrium states is important for the simulation of condensed matter and cosmology systems using a quantum computer. We present a method to prepare such mixed states with unitary operators and demonstrate this technique experimentally using a gate-based quantum processor. Our method targets the generation of thermofield double states using a hybrid quantum-classical variational approach motivated by quantum-approximate optimization algorithms, without prior calculation of optimal variational parameters by numerical simulation. The fidelity of generated states to the thermal-equilibrium state smoothly varies from 99 to 75% between infinite and near-zero simulated temperature, in quantitative agreement with numerical simulations of the noisy quantum processor with error parameters drawn from experiment.

Future fault-tolerant quantum computers will require storing and processing quantum data in logical qubits. Here we realize a suite of logical operations on a distance-2 surface code qubit built from seven physical qubits and stabilized using repeated error-detection cycles. Logical operations include initialization into arbitrary states, measurement in the cardinal bases of the Bloch sphere and a universal set of single-qubit gates. For each type of operation, we observe higher performance for fault-tolerant variants over non-fault-tolerant variants, and quantify the difference. In particular, we demonstrate process tomography of logical gates, using the notion of a logical Pauli transfer matrix. This integration of high-fidelity logical operations with a scalable scheme for repeated stabilization is a milestone on the road to quantum error correction with higher-distance superconducting surface codes.

Simple tuneup of fast two-qubit gates is essential for the scaling of quantum processors. We introduce the sudden variant (SNZ) of the net zero scheme realizing controlled-Z (CZ) gates by flux control of transmon frequency. SNZ CZ gates realized in a multitransmon processor operate at the speed limit of transverse coupling between computational and noncomputational states by maximizing intermediate leakage. Beyond speed, the key advantage of SNZ is tuneup simplicity, owing to the regular structure of conditional phase and leakage as a function of two control parameters. SNZ is compatible with scalable schemes for quantum error correction and adaptable to generalized conditional-phase gates useful in intermediate-scale applications.

Variational quantum eigensolvers offer a small-scale testbed to demonstrate the performance of error mitigation techniques with low experimental overhead. We present successful error mitigation by applying the recently proposed symmetry verification technique to the experimental estimation of the ground-state energy and ground state of the hydrogen molecule. A finely adjustable exchange interaction between two qubits in a circuit QED processor efficiently prepares variational ansatz states in the single-excitation subspace respecting the parity symmetry of the qubit-mapped Hamiltonian. Symmetry verification improves the energy and state estimates by mitigating the effects of qubit relaxation and residual qubit excitation, which violate the symmetry. A full-density-matrix simulation matching the experiment dissects the contribution of these mechanisms from other calibrated error sources. Enforcing positivity of the measured density matrix via scalable convex optimization correlates the energy and state estimate improvements when using symmetry verification, with interesting implications for determining system properties beyond the ground-state energy.