Automated Testing of Interlockings in Digital Substations

Abstract

This thesis proposes an automated method for generating, executing, and assessing an interlocking test in a digital substation using a Python script designed for that specific purpose.

The goal is to expedite the process of performing the factory acceptance test (FAT) and the site acceptance test (SAT) of a substation automation system (SAS). This work requires a good understanding of the IEC 61850 standard, which is the international standard applicable to protection, automation and control systems (PACS). An account of the relevant parts from this series is therefore given, in addition to an overview of the benefits of digital substations in general.

The workflow for automatically generating a test case is based on previous work that made it possible to execute and assess an interlocking test automatically but not to generate a test case automatically for this purpose. Therefore, that is the main intention of the thesis.

It is done by having knowledge of the underlying interlocking logic of the system subject to test. From this logic, a test sequence can be created, where the position of the various switchgear is changed sequentially. This and the signal addresses for these devices are needed to generate a test case.

For additional robustness, the script can cross-check the signal addresses provided with the signal addresses in the substation configuration description (SCD) file and validate the final test case generated using a suitable schema. It is furthermore capable of generating a test case irrespective of the number of test steps, switching devices, and bays present in the substation.

A test file generated using this script is further validated by executing the test it describes in the SAS laboratory at the Norwegian University of Science and Technology (NTNU). This test was carried out remotely to showcase the possibilities of IEC 61850, which can be valuable for distant or offshore substations. Another benefit of this workflow is that it allows for the simulation of all devices of the test except for the device under test (DUT). This is particularly useful during commissioning if all devices have not yet been delivered or installed. In this case, the missing equipment can be compensated for by simulating the signals expected from these devices.

The final assessment of a test case relies upon the presence of the IEC 61850 LN (Logical Node) CILO (Control Interlocking). The output of this LN controls the interlock status of the DUT. If the DUT is allowed to operate, it sends a release signal or, alternatively, a blocking signal. In addition to this, information is gained based on the position of the switchgear under test to check that the CILO signal is consistent with the actual switchgear control command. This control command is known as the AddCause in IEC 61850 and will provide additional information on whether or not the DUT is interlocked.

Finally, the thesis will describe ongoing work in the IEC 61850 that could lead to a more streamlined approach and touch on the utilities' attitude towards SAS.