Versatile DAC-less successive approximation ADC architecture for medium speed data acquisition

Abstract

Implementation of the DAC is usually the bottleneck in designing a SAR ADC. Here an innovative DAC-less SAR (DLSAR) ADC architecture is presented which alleviates some drawbacks of the conventional SAR counterpart. The proposed DLSAR binary search algorithm is comprised of two arithmetic operations of division-by-two and subtraction to emulate the DAC function. The hardware of the DLSAR ADC is implemented using ordinary circuit building blocks of a SAR ADC but with less complexity and more robustness against PVT variations as DAC is removed. The developed DLSAR architecture is versatile so that the converter hardware could be readily reconfigured for different sampling rates and resolutions. Based on post-layout simulations in 0.18 μm CMOS process, the designed 8-bit DLSAR ADC consumes 150 μW of power at 2 MS/s including the asynchronous control logic circuit. The SFDR of the converter is up to 62 dB and the ENOB reaches 7.8 bits while it remains above 7.5 bits across most PVT corners without calibration. Also, by reconfiguring the DLSAR ADC to 9-bit resolution at 1 MS/s, the ENOB is generally around 8.2 bits achieving a scaled figure-of-merit (SFoM) better than 3.0 Ç/c-s.