An Area- and Energy-Efficient Ultrasonic Pulser Based on Self-timed Stepwise Charging

Abstract

Acoustoelectric imaging is an emerging technology confirmed by in-vivo experiments that can help diagnose and evaluate peripheral nerve neuropathy. The ultrasound transmitter (TX) is required in such systems to selectively focus and apply acoustic pressure on the target volume. Within the ultrasound TX, the power amplifier (PA, commonly called pulser) can dominate up to 99\% of total TX power consumption. In this case, the pulser must be power-efficient and integrated with modern complementary metal-oxide semiconductor (CMOS) compatible transducers to enable miniaturized AE imaging systems. However, the small form factor is the natural limit for high-energy-efficiency pulser design.

The class-D switched-mode PA is the most common approach to drive ultrasonic transducers in recent research publications and commercialized products (e.g., TUSS
4470 by Texas Instruments$^\text{TM}$, STHVUP32 by STMicroelectronics$^\text{TM}$). Although the class-D PA manifests inherently simple and area-efficient features, it suffers from power loss on switching the plate parasitic capacitor $C_p$ of the transducer. Prior arts use excessive off-chip capacitors, inductors, and high-frequency switch-clocking signals generated by frequency synthesizers to switch the PA in different configurations to save power on $C_p$. However, these approaches increase the system form factor and introduce high-speed clock routing. Additionally, efforts to flip and short both terminals of the transducer for increased PA efficiency are not practical for CMOS-compatible transducer arrays. The trade-offs involved in optimizing switched-mode pulser efficiency extend beyond a simple consideration of $C_p$.

This work proposes a new baseline power-efficiency analysis that comprehensively explains the switched-mode PA efficiency considering transducer characteristics. A switched-mode pulser based on the stepwise-charging technique, controlled by a stepwise sequencer based on a symmetrically-modulated delay cell, is implemented in 130 nm technology. The proposed architecture achieves an overall acoustic efficiency of 82.5\% in simulation while maintaining an average efficiency of 81\% in global PVT and mismatch corners. The PA achieves a 9.9\% acoustic-efficiency improvement compared to its baseline and significantly outperforms the work with a similar baseline by 6.9\%. The achieved efficiency is also comparable to the work featuring a 9.1\% higher baseline, while this work demonstrates a 20x saving in capacitance budget. The PA signal chain is estimated to have an area of 108 $\mu$m x 520 $\mu$m, which can be fit into a 115$\mu$m-pitch 1-D transducer channel without extra reference resources, offering promising prospects for compact multi-channel integrations.