A 4 GHz Continuous-Time ΔΣ ADC With 70dB DR and -74dBFS THD in 125MHz BW

Journal article (2011)

Authors

M. Bolatkale NXP Semiconductors

LJ Breems Electronic Instrumentation -

Robert Rutten NXP Semiconductors

K.A.A. Makinwa Electronic Instrumentation -

Kofi A.A. Makinwa Electronic Instrumentation -

Research Group

Electronic Instrumentation () (TU Delft)

DOI: https://doi.org/10.1109/JSSC.2011.2164963

Wireless communication Delta-sigma modulator CMOS analog integrated circuits Analog-to-digital conversion Base stations Continuous-time filters Continuous-time sigma-delta modulation Multi-bit Oversampling ADCs Radio receivers

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Published Date

2011

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Instrumentation

Abstract

A 4 GHz third-order continuous-time ΔΣ ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer's latency. The ADC was implemented in 45 nm-LP CMOS and achieves 70 dB DR and -74 dBFS THD in a 125 MHz BW, while dissipating 260 mW from 1.1/1.8 V supply. The ADC occupies 0.9 mm 2 including the modulator, clock circuitry and decimation filter.

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